[PATCH v5 02/15] dt-bindings: mmc: cdns: Add AMD Pensando Elba SoC binding
Rob Herring
robh at kernel.org
Tue Jun 14 14:22:15 PDT 2022
On Mon, Jun 13, 2022 at 12:56:45PM -0700, Brad Larson wrote:
> From: Brad Larson <blarson at amd.com>
>
> AMD Pensando Elba ARM 64-bit SoC is integrated with this IP and
> explicitly controls byte-lane enables.
>
> Signed-off-by: Brad Larson <blarson at amd.com>
> ---
> .../devicetree/bindings/mmc/cdns,sdhci.yaml | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
> index 4207fed62dfe..35bc4cf6f214 100644
> --- a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
> +++ b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
> @@ -13,10 +13,24 @@ maintainers:
> allOf:
> - $ref: mmc-controller.yaml
>
> + - if:
> + properties:
> + compatible:
> + enum:
> + - amd,pensando-elba-sd4hc
> + then:
> + properties:
> + reg:
> + items:
> + - description: Cadence host controller registers
> + - description: Byte-lane control register
> + minItems: 2
This doesn't work. The if/then is additional constraints on the main
section which says there is only 1 register region. The main section
needs the above, but with 'minItems: 1'. Then the if/then should be:
if:
properties:
compatible:
const: amd,pensando-elba-sd4hc
then:
properties:
reg:
minItems: 2
else:
properties:
reg:
maxItems: 1
> +
> properties:
> compatible:
> items:
> - enum:
> + - amd,pensando-elba-sd4hc
> - microchip,mpfs-sd4hc
> - socionext,uniphier-sd4hc
> - const: cdns,sd4hc
> --
> 2.17.1
>
>
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