[PATCHv2] iommu/arm-smmu-qcom: Add debug support for TLB sync timeouts

[Sai Prakash Ranjan]

Hi Vincent,

On 6/9/2022 2:52 AM, Vincent Knecht wrote:
> Le jeudi 26 mai 2022 à 09:44 +0530, Sai Prakash Ranjan a écrit :
>> TLB sync timeouts can be due to various reasons such as TBU power down
>> or pending TCU/TBU invalidation/sync and so on. Debugging these often
>> require dumping of some implementation defined registers to know the
>> status of TBU/TCU operations and some of these registers are not
>> accessible in non-secure world such as from kernel and requires SMC
>> calls to read them in the secure world. So, add this debug support
>> to dump implementation defined registers for TLB sync timeout issues.
>>
>> Signed-off-by: Sai Prakash Ranjan <quic_saipraka at quicinc.com>
>> ---
>>
>> Changes in v2:
>>   * Use scm call consistently so that it works on older chipsets where
>>     some of these regs are secure registers.
>>   * Add device specific data to get the implementation defined register
>>     offsets.
>>
>> ---
>>   drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 161 ++++++++++++++++++---
>>   drivers/iommu/arm/arm-smmu/arm-smmu.c      |   2 +
>>   drivers/iommu/arm/arm-smmu/arm-smmu.h      |   1 +
>>   3 files changed, 146 insertions(+), 18 deletions(-)
> Hi Sai, and thanks for this patch !
>
> I've encountered TLB sync timeouts with msm8939 SoC recently.
> What would be needed to add to this patch so this SoC is supported ?
> Like, where could one check the values to be used in an equivalent
> of qcom_smmu_impl0_reg_offset values for this SoC (if any change needed) ?
> Current values are not found by simply greping in downstream/vendor dtsi/dts files...

These are implementation defined registers and some might not be present on older SoCs
and sometimes they don't add this support in downstream kernels even if the registers
are present.

I looked up the IP doc for msm8939 and I could find only TBU_PWR_STATUS register and
you can use the same offset for it as given in this patch.

Thanks,
Sai