[PATCH v2 17/17] arm64/sysreg: Convert ID_AA64ISAR2_EL1 to automatic generation

[Joey Gouly]

Hi Mark,

On Wed, Jun 08, 2022 at 02:31:51PM +0100, Mark Brown wrote:
> Automatically generate defines for ID_AA64ISAR2_EL1, using the definitions
> in DDI0487H.a. No functional changes.
> 
> Signed-off-by: Mark Brown <broonie at kernel.org>
> ---
>  arch/arm64/include/asm/sysreg.h | 27 ---------------------------
>  arch/arm64/tools/sysreg         | 33 +++++++++++++++++++++++++++++++++
>  2 files changed, 33 insertions(+), 27 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 6a732dba73ac..767f5392ba3d 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -201,8 +201,6 @@
>  #define SYS_ID_AA64AFR0_EL1		sys_reg(3, 0, 0, 5, 4)
>  #define SYS_ID_AA64AFR1_EL1		sys_reg(3, 0, 0, 5, 5)
>  
> -#define SYS_ID_AA64ISAR2_EL1		sys_reg(3, 0, 0, 6, 2)
> -
>  #define SYS_ID_AA64MMFR0_EL1		sys_reg(3, 0, 0, 7, 0)
>  #define SYS_ID_AA64MMFR1_EL1		sys_reg(3, 0, 0, 7, 1)
>  #define SYS_ID_AA64MMFR2_EL1		sys_reg(3, 0, 0, 7, 2)
> @@ -699,31 +697,6 @@
>  /* Position the attr at the correct index */
>  #define MAIR_ATTRIDX(attr, idx)		((attr) << ((idx) * 8))
>  
> -/* id_aa64isar2 */
> -#define ID_AA64ISAR2_EL1_BC_SHIFT		28
> -#define ID_AA64ISAR2_EL1_APA3_SHIFT		12
> -#define ID_AA64ISAR2_EL1_GPA3_SHIFT		8
> -#define ID_AA64ISAR2_EL1_RPRES_SHIFT	4
> -#define ID_AA64ISAR2_EL1_WFxT_SHIFT		0
> -
> -/*
> - * Value 0x1 has been removed from the architecture, and is
> - * reserved, but has not yet been removed from the ARM ARM
> - * as of ARM DDI 0487G.b.
> - */
> -#define ID_AA64ISAR2_EL1_WFxT_NI		0x0
> -#define ID_AA64ISAR2_EL1_WFxT_IMP		0x2
> -
> -#define ID_AA64ISAR2_EL1_APA3_NI			0x0
> -#define ID_AA64ISAR2_EL1_APA3_PAuth			0x1
> -#define ID_AA64ISAR2_EL1_APA3_EPAC			0x2
> -#define ID_AA64ISAR2_EL1_APA3_PAuth2			0x3
> -#define ID_AA64ISAR2_EL1_APA3_FPAC			0x4
> -#define ID_AA64ISAR2_EL1_APA3_FPACCOMBINE		0x5
> -
> -#define ID_AA64ISAR2_EL1_GPA3_NI			0x0
> -#define ID_AA64ISAR2_EL1_GPA3_IMP			0x1
> -
>  /* id_aa64pfr0 */
>  #define ID_AA64PFR0_CSV3_SHIFT		60
>  #define ID_AA64PFR0_CSV2_SHIFT		56
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index 29d081b3dcd2..0c949857e371 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -193,6 +193,39 @@ Enum	3:0	DPB
>  	0b0010	DPB2
>  EndEnum
>  EndSysreg
> +
> +Sysreg	ID_AA64ISAR2_EL1	3	0	0	6	2
> +Res0	63:28
> +Enum	27:24	PAC_frac
> +	0b0000	NI
> +	0b0001	IMP
> +EndEnum
> +Enum	23:20	BC
> +	0b0000	NI
> +	0b0001	IMP
> +EndEnum
> +Enum	19:16	MOPS
> +	0b0000	NI
> +	0b0001	IMP
> +EndEnum
> +Enum	15:12	APA3
> +	0b0000	NI
> +	0b0001	PAuth
> +	0b0010	EPAC
> +	0b0011	PAuth2
> +	0b0100	FPAC
> +	0b0101	FPACCOMBINE
> +EndEnum
> +Enum	11:8	GPA3
> +	0b0000	NI
> +	0b0001	IMP
> +EndEnum
> +Enum	7:4	RPRES
> +	0b0000	NI
> +	0b0001	IMP
> +EndEnum
> +Enum	3:0	WFxT
> +	0b0000	NI
>  	0b0001	IMP


This should be 0b0010. It was 0b0001 in older versions of the spec.

>From DDI 0487H.a, D13-5676:

	0b0000 WFET and WFIT are not supported.
	0b0010 WFET and WFIT are supported, and the register number is reported in the ESR_ELx on exceptions.
	All other values are reserved.

Thanks,
Joey