[PATCH v1 13/17] arm64/sysreg: Generate defines for CTR_EL0

[Mark Brown]

Convert CTR_EL0 to automatic register generation as per DDI0487H.a, no
functional change.

Signed-off-by: Mark Brown <broonie at kernel.org>
---
 arch/arm64/include/asm/sysreg.h | 17 -----------------
 arch/arm64/tools/sysreg         | 20 ++++++++++++++++++++
 2 files changed, 20 insertions(+), 17 deletions(-)

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 739f55cf9cd8..03d35c1e7e43 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -461,7 +461,6 @@
 #define SMIDR_EL1_SMPS_SHIFT	15
 #define SMIDR_EL1_AFFINITY_SHIFT	0
 
-#define SYS_CTR_EL0			sys_reg(3, 3, 0, 0, 1)
 #define SYS_DCZID_EL0			sys_reg(3, 3, 0, 0, 7)
 
 #define SYS_RNDR_EL0			sys_reg(3, 3, 2, 4, 0)
@@ -1082,22 +1081,6 @@
 #define MVFR2_FPMISC_SHIFT		4
 #define MVFR2_SIMDMISC_SHIFT		0
 
-#define CTR_EL0_L1Ip_VPIPT		0
-#define CTR_EL0_L1Ip_AIVIVT		1
-#define CTR_EL0_L1Ip_VIPT		2
-#define CTR_EL0_L1Ip_PIPT		3
-
-#define CTR_EL0_L1Ip_SHIFT		14
-#define CTR_EL0_L1Ip_MASK		3
-#define CTR_EL0_DminLine_SHIFT		16
-#define CTR_EL0_IminLine_SHIFT		0
-#define CTR_EL0_IminLine_MASK		0xf
-#define CTR_EL0_ERG_SHIFT		20
-#define CTR_EL0_CWG_SHIFT		24
-#define CTR_EL0_CWG_MASK		15
-#define CTR_EL0_IDC_SHIFT		28
-#define CTR_EL0_DIC_SHIFT		29
-
 #define DCZID_EL0_DZP_SHIFT		4
 #define DCZID_EL0_BS_SHIFT		0
 
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index ff5e552f7420..3c58aa57d672 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -273,6 +273,26 @@ Field	3:1	Level
 Field	0	InD
 EndSysreg
 
+Sysreg	CTR_EL0	3	3	0	0	1
+Res0	63:38
+Field	37:32	TminLine
+Res1	31
+Res0	30
+Field	29	DIC
+Field	28	IDC
+Field	27:24	CWG
+Field	23:20	ERG
+Field	19:16	DminLine
+Enum	15:14	L1Ip
+	0b00	VPIPT
+	0b01	AIVIVT
+	0b10	VIPT
+	0b11	PIPT
+EndEnum
+Res0	13:4
+Field	3:0	IminLine
+EndSysreg
+
 Sysreg	SVCR	3	3	4	2	2
 Res0	63:2
 Field	1	ZA
-- 
2.30.2