[PATCH] phy: samsung: exynosautov9-ufs: correct TSRV register configurations

[Alim Akhtar]

>-----Original Message-----
>From: Chanho Park [mailto:chanho61.park at samsung.com]
>Sent: Tuesday, May 31, 2022 1:57 PM
>To: Kishon Vijay Abraham I <kishon at ti.com>; Vinod Koul
><vkoul at kernel.org>; Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>;
>Alim Akhtar <alim.akhtar at samsung.com>
>Cc: linux-phy at lists.infradead.org; linux-arm-kernel at lists.infradead.org;
>Chanho Park <chanho61.park at samsung.com>
>Subject: [PATCH] phy: samsung: exynosautov9-ufs: correct TSRV register
>configurations
>
>For exynos auto v9's UFS MPHY, We should use 0x50 offset of TSRV register
>configurations. So, it must be
>
>s/PHY_TRSV_REG_CFG/PHY_TRSV_REG_CFG/g
>


You mean

s/PHY_TRSV_REG_CFG/PHY_TRSV_REG_CFG_AUTOV9/g

>Fixes: d64519249e1d ("phy: samsung-ufs: support exynosauto ufs phy driver")
>Signed-off-by: Chanho Park <chanho61.park at samsung.com>
>---
> drivers/phy/samsung/phy-exynosautov9-ufs.c | 18 +++++++++---------
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
>diff --git a/drivers/phy/samsung/phy-exynosautov9-ufs.c
>b/drivers/phy/samsung/phy-exynosautov9-ufs.c
>index 36398a15c2db..d043dfdb598a 100644
>--- a/drivers/phy/samsung/phy-exynosautov9-ufs.c
>+++ b/drivers/phy/samsung/phy-exynosautov9-ufs.c
>@@ -31,22 +31,22 @@ static const struct samsung_ufs_phy_cfg
>exynosautov9_pre_init_cfg[] = {
> 	PHY_COMN_REG_CFG(0x023, 0xc0, PWR_MODE_ANY),
> 	PHY_COMN_REG_CFG(0x023, 0x00, PWR_MODE_ANY),
>
>-	PHY_TRSV_REG_CFG(0x042, 0x5d, PWR_MODE_ANY),
>-	PHY_TRSV_REG_CFG(0x043, 0x80, PWR_MODE_ANY),
>+	PHY_TRSV_REG_CFG_AUTOV9(0x042, 0x5d, PWR_MODE_ANY),
>+	PHY_TRSV_REG_CFG_AUTOV9(0x043, 0x80, PWR_MODE_ANY),
>
> 	END_UFS_PHY_CFG,
> };
>
> /* Calibration for HS mode series A/B */  static const struct
>samsung_ufs_phy_cfg exynosautov9_pre_pwr_hs_cfg[] = {
>-	PHY_TRSV_REG_CFG(0x032, 0xbc, PWR_MODE_HS_ANY),
>-	PHY_TRSV_REG_CFG(0x03c, 0x7f, PWR_MODE_HS_ANY),
>-	PHY_TRSV_REG_CFG(0x048, 0xc0, PWR_MODE_HS_ANY),
>+	PHY_TRSV_REG_CFG_AUTOV9(0x032, 0xbc, PWR_MODE_HS_ANY),
>+	PHY_TRSV_REG_CFG_AUTOV9(0x03c, 0x7f, PWR_MODE_HS_ANY),
>+	PHY_TRSV_REG_CFG_AUTOV9(0x048, 0xc0, PWR_MODE_HS_ANY),
>
>-	PHY_TRSV_REG_CFG(0x04a, 0x00, PWR_MODE_HS_G3_SER_B),
>-	PHY_TRSV_REG_CFG(0x04b, 0x10, PWR_MODE_HS_G1_SER_B |
>-				      PWR_MODE_HS_G3_SER_B),
>-	PHY_TRSV_REG_CFG(0x04d, 0x63, PWR_MODE_HS_G3_SER_B),
>+	PHY_TRSV_REG_CFG_AUTOV9(0x04a, 0x00,
>PWR_MODE_HS_G3_SER_B),
>+	PHY_TRSV_REG_CFG_AUTOV9(0x04b, 0x10,
>PWR_MODE_HS_G1_SER_B |
>+				PWR_MODE_HS_G3_SER_B),
>+	PHY_TRSV_REG_CFG_AUTOV9(0x04d, 0x63,
>PWR_MODE_HS_G3_SER_B),
>
> 	END_UFS_PHY_CFG,
> };
>--
>2.36.1