[EXT] Re: [PATCH v3 3/4] dt-bindings: irqchip: imx mu work as msi controller
Krzysztof Kozlowski
krzysztof.kozlowski at linaro.org
Mon Jul 25 13:28:11 PDT 2022
On 25/07/2022 18:55, Frank Li wrote:
>>>> Not minItems but maxItems in general, but anyway you need to actually
>>>> list and describe the items (and then skip min/max)
>>> [Frank Li]
>>> I am not sure format. Any example?
>>>
>>> Reg:
>>> Items:
>>> - description: a side register
>>> - description: b side register
>>
>> Yes, but then explain what is A and B in bindings description.
>
> [Frank Li] How about "A(B) side base register address."
> Any other description need?
In top-level description you have:
"The MU also provides the ability for one processor to signal the
other processor using interrupts."
so maybe:
"The MU also provides the ability for one processor (A side) to signal
the other processor (B side) using interrupts."
>
>>
>> Why MU, which sits on A side needs to access other side (B) registers?
>
> [Frank Li] MU work as MSI controller for PCI EP. So driver need provide
> B side register to PCI EP by msi_msg. PCI EP driver use this address to set
> PCI bar<n>. Then PCI host can write this address to trigger PCIe EP side irq
> As doorbell.
>
> MU MSI driver also need A side register
> To get irq status. So MU MSI need both side registers.
OK.
Best regards,
Krzysztof
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