[EXT] Re: [PATCH v3 3/4] dt-bindings: irqchip: imx mu work as msi controller

[Frank Li]

> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
> Sent: Saturday, July 23, 2022 1:50 PM
> To: Frank Li <frank.li at nxp.com>; jdmason at kudzu.us; maz at kernel.org;
> tglx at linutronix.de; robh+dt at kernel.org; krzysztof.kozlowski+dt at linaro.org;
> shawnguo at kernel.org; s.hauer at pengutronix.de; kw at linux.com;
> bhelgaas at google.com
> Cc: kernel at vger.kernel.org; devicetree at vger.kernel.org; linux-arm-
> kernel at lists.infradead.org; linux-pci at vger.kernel.org; Peng Fan
> <peng.fan at nxp.com>; Aisheng Dong <aisheng.dong at nxp.com>;
> kernel at pengutronix.de; festevam at gmail.com; dl-linux-imx <linux-
> imx at nxp.com>; kishon at ti.com; lorenzo.pieralisi at arm.com;
> ntb at lists.linux.dev
> Subject: [EXT] Re: [PATCH v3 3/4] dt-bindings: irqchip: imx mu work as msi
> controller
> 
> Caution: EXT Email
> 
> On 20/07/2022 23:30, Frank Li wrote:
> > imx mu support generate irq by write a register.
> > provide msi controller support so other driver
> > can use it by standard msi interface.
> 
> Please start sentences with capital letter. Unfortunately I don't
> understand the sentences. Please describe shortly the hardware.

[Frank Li]  MU have 4 registers and both side A and B.  If write one of
Register,  irq will be trigger at the other side. 

For example,  writle(a side reg1, 0).  Then b side irq will be trigged. 

> 
> 
> >
> > Signed-off-by: Frank Li <Frank.Li at nxp.com>
> > ---
> >  .../interrupt-controller/fsl,mu-msi.yaml      | 88 +++++++++++++++++++
> >  1 file changed, 88 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/interrupt-
> controller/fsl,mu-msi.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-
> msi.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-
> msi.yaml
> > new file mode 100644
> > index 0000000000000..e125294243af3
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-
> msi.yaml
> > @@ -0,0 +1,88 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id:
> https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicet
> ree.org%2Fschemas%2Finterrupt-controller%2Ffsl%2Cmu-
> msi.yaml%23&data=05%7C01%7CFrank.Li%40nxp.com%7Cfcec12a0731c
> 454af5c308da6cdc2a0e%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0
> %7C637941990101591376%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLj
> AwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%
> 7C%7C&sdata=9h9nKyvsWaghry1hkpa5aaxVGYpx6xZRTxhN0S4uB50%3
> D&reserved=0
> > +$schema:
> https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicet
> ree.org%2Fmeta-
> schemas%2Fcore.yaml%23&data=05%7C01%7CFrank.Li%40nxp.com%7
> Cfcec12a0731c454af5c308da6cdc2a0e%7C686ea1d3bc2b4c6fa92cd99c5c3016
> 35%7C0%7C0%7C637941990101591376%7CUnknown%7CTWFpbGZsb3d8eyJ
> WIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%
> 7C3000%7C%7C%7C&sdata=wagM3hl8fpJSm%2Bibw6ENl5lNlQ9fVEHzS
> OlT%2Bjoridg%3D&reserved=0
> > +
> > +title: NXP i.MX Messaging Unit (MU) work as msi controller
> > +
> > +maintainers:
> > +  - Frank Li <Frank.Li at nxp.com>
> > +
> > +description: |
> > +  The Messaging Unit module enables two processors within the SoC to
> > +  communicate and coordinate by passing messages (e.g. data, status
> > +  and control) through the MU interface. The MU also provides the ability
> > +  for one processor to signal the other processor using interrupts.
> > +
> > +  Because the MU manages the messaging between processors, the MU
> uses
> > +  different clocks (from each side of the different peripheral buses).
> > +  Therefore, the MU must synchronize the accesses from one side to the
> > +  other. The MU accomplishes synchronization using two sets of matching
> > +  registers (Processor A-facing, Processor B-facing).
> > +
> > +  MU can work as msi interrupt controller to do doorbell
> > +
> > +allOf:
> > +  - $ref: /schemas/interrupt-controller/msi-controller.yaml#
> > +
> > +properties:
> > +  compatible:
> > +    enum:
> > +      - fsl,imx6sx-mu-msi
> > +      - fsl,imx7ulp-mu-msi
> > +      - fsl,imx8ulp-mu-msi
> > +      - fsl,imx8ulp-mu-msi-s4
> > +
> > +  reg:
> > +    minItems: 2
> 
> Not minItems but maxItems in general, but anyway you need to actually
> list and describe the items (and then skip min/max)
[Frank Li] 
	I am not sure format.  Any example?

Reg:
      Items:
           - description:  a side register
           - description: b side register
> 
> > +
> > +  reg-names:
> > +    items:
> > +      - const: a
> > +      - const: b
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +
> > +  clocks:
> > +    maxItems: 1
> > +
> > +  power-domains:
> > +    maxItems: 2
> 
> and here you correctly use maxItems, so why min in reg? Anyway, instead
> you need to list and describe the items.
 
Does format is similar with reg?
	
> 
> Actually I asked you this last time about interrupts, so you ignored
> that comment.

Sorry, which one. Is it below one?  

---
> +  interrupts:
> +    minItems: 1
> +    maxItems: 2

Instead describe the items.
---

> 
> > +
> > +  power-domain-names:
> > +    items:
> > +      - const: a
> > +      - const: b
> > +
> > +  interrupt-controller: true
> > +
> > +  msi-controller: true
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - interrupts
> > +  - msi-controller
> > +  - interrupt-controller
> 
> Why different order than used in properties?
> 
> 
> 
> Best regards,
> Krzysztof