[PATCH net-next v3 46/47] arm64: dts: ls1046ardb: Add serdes bindings

[Sean Anderson]

On 7/21/22 10:20 AM, Camelia Alexandra Groza wrote:
>> -----Original Message-----
>> From: Sean Anderson <sean.anderson at seco.com>
>> Sent: Saturday, July 16, 2022 1:00
>> To: David S . Miller <davem at davemloft.net>; Jakub Kicinski
>> <kuba at kernel.org>; Madalin Bucur <madalin.bucur at nxp.com>;
>> netdev at vger.kernel.org
>> Cc: Paolo Abeni <pabeni at redhat.com>; Eric Dumazet
>> <edumazet at google.com>; linux-arm-kernel at lists.infradead.org; Russell
>> King <linux at armlinux.org.uk>; linux-kernel at vger.kernel.org; Sean Anderson
>> <sean.anderson at seco.com>; Kishon Vijay Abraham I <kishon at ti.com>;
>> Krzysztof Kozlowski <krzysztof.kozlowski+dt at linaro.org>; Leo Li
>> <leoyang.li at nxp.com>; Rob Herring <robh+dt at kernel.org>; Shawn Guo
>> <shawnguo at kernel.org>; Vinod Koul <vkoul at kernel.org>;
>> devicetree at vger.kernel.org; linux-phy at lists.infradead.org
>> Subject: [PATCH net-next v3 46/47] arm64: dts: ls1046ardb: Add serdes
>> bindings
>> 
>> This adds appropriate bindings for the macs which use the SerDes. The
>> 156.25MHz fixed clock is a crystal. The 100MHz clocks (there are
>> actually 3) come from a Renesas 6V49205B at address 69 on i2c0. There is
>> no driver for this device (and as far as I know all you can do with the
>> 100MHz clocks is gate them), so I have chosen to model it as a single
>> fixed clock.
>> 
>> Note: the SerDes1 lane numbering for the LS1046A is *reversed*.
>> This means that Lane A (what the driver thinks is lane 0) uses pins
>> SD1_TX3_P/N.
>> 
>> Because this will break ethernet if the serdes is not enabled, enable
>> the serdes driver by default on Layerscape.
>> 
>> Signed-off-by: Sean Anderson <sean.anderson at seco.com>
>> ---
>> Please let me know if there is a better/more specific config I can use
>> here.
>> 
>> (no changes since v1)
> 
> My LS1046ARDB hangs at boot with this patch right after the second SerDes is probed,
> right before the point where the PCI host bridge is registered. I can get around this
> either by disabling the second SerDes node from the device tree, or disabling
> CONFIG_PCI_LAYERSCAPE at build.
> 
> I haven't debugged it more but there seems to be an issue here.

Hm. Do you have anything plugged into the PCIe/SATA slots? I haven't been testing with
anything there. For now, it may be better to just leave it disabled.

--Sean