[PATCH 06/12] clk: sunxi=ng: add support for R329 CCUs
Icenowy Zheng
icenowy at aosc.io
Tue Jul 12 04:57:29 PDT 2022
在 2022-04-23星期六的 21:12 -0500,Samuel Holland写道:
> On 4/22/22 10:41 AM, icenowy at outlook.com wrote:
> > From: Icenowy Zheng <icenowy at aosc.io>
> >
> > Allwinner R329 has two CCUs, one in CPUX and another in PRCM.
> >
> > Add support for them.
> >
> > Signed-off-by: Icenowy Zheng <icenowy at aosc.io>
>
> There is a typo in your commit title. = should be -.
>
> Thanks for updating the driver to use .fw_name and be loadable as a
> module. All
> of those changes look good.
>
> There are still some missing clocks here compared to the BSP, and a
> couple of
> other minor issues. Please see my earlier review:
>
> https://lore.kernel.org/linux-sunxi/99a74950-fdc0-ecfe-e5f0-ba4a7d8751f0@sholland.org/
>
> So far it's been consistent that any settable bits in the CCU
> registers actually
> do something. So I would expect all of those bits to have an index
> reserved in
> the binding, even if we do not model them. I want to avoid having to
Sorry but I don't think it proper to reserve unclear bits, because
we're just allocating the numbers as a random sequence (in fact it's
the sequence that it gets implemented).
Or consider a structural number scheme, in which a value can be
uniquely predicted by its name?
> go back and
> add gates to the binding out-of-order later, like we are doing for
> H6.
>
> Regards,
> Samuel
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