[PATCH v2 1/2] ARM: Marvell: Update PCIe fixup

Thu Jul 7 11:31:12 PDT 2022

PING? I have not received any reply!

On Saturday 14 May 2022 20:21:25 Pali Rohár wrote:
> On Tuesday 09 November 2021 23:53:32 Pali Rohár wrote:
> > On Tuesday 02 November 2021 18:12:58 Pali Rohár wrote:
> > > - The code relies on rc_pci_fixup being called, which only happens
> > >   when CONFIG_PCI_QUIRKS is enabled, so add that to Kconfig. Omitting
> > >   this causes a booting failure with a non-obvious cause.
> > > - Update rc_pci_fixup to set the class properly, copying the
> > >   more modern style from other places
> > > - Correct the rc_pci_fixup comment
> > > 
> > > This patch just re-applies commit 1dc831bf53fd ("ARM: Kirkwood: Update
> > > PCI-E fixup") for all other Marvell ARM platforms which have same buggy
> > > PCIe controller and do not use pci-mvebu.c controller driver yet.
> > > 
> > > Long-term goal for these Marvell ARM platforms should be conversion to
> > > pci-mvebu.c controller driver and removal of these fixups in arch code.
> > > 
> > > Signed-off-by: Pali Rohár <pali at kernel.org>
> > > Cc: Jason Gunthorpe <jgg at nvidia.com>
> > > Cc: stable at vger.kernel.org
> > 
> > Hello! Patch 2/2 was already applied into mips-next. Could you review
> > also this patch 1/2?
> 
> PING?
> 
> > > 
> > > ---
> > > Changes in v2:
> > > * Move MIPS change into separate patch
> > > * Add information that this patch is for platforms which do not use pci-mvebu.c
> > > ---
> > >  arch/arm/Kconfig              |  1 +
> > >  arch/arm/mach-dove/pcie.c     | 11 ++++++++---
> > >  arch/arm/mach-mv78xx0/pcie.c  | 11 ++++++++---
> > >  arch/arm/mach-orion5x/Kconfig |  1 +
> > >  arch/arm/mach-orion5x/pci.c   | 12 +++++++++---
> > >  5 files changed, 27 insertions(+), 9 deletions(-)
> > > 
> > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> > > index fc196421b2ce..9f157e973555 100644
> > > --- a/arch/arm/Kconfig
> > > +++ b/arch/arm/Kconfig
> > > @@ -400,6 +400,7 @@ config ARCH_DOVE
> > >  	select GENERIC_IRQ_MULTI_HANDLER
> > >  	select GPIOLIB
> > >  	select HAVE_PCI
> > > +	select PCI_QUIRKS if PCI
> > >  	select MVEBU_MBUS
> > >  	select PINCTRL
> > >  	select PINCTRL_DOVE
> > > diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c
> > > index ee91ac6b5ebf..ecf057a0f5ba 100644
> > > --- a/arch/arm/mach-dove/pcie.c
> > > +++ b/arch/arm/mach-dove/pcie.c
> > > @@ -135,14 +135,19 @@ static struct pci_ops pcie_ops = {
> > >  	.write = pcie_wr_conf,
> > >  };
> > >  
> > > +/*
> > > + * The root complex has a hardwired class of PCI_CLASS_MEMORY_OTHER, when it
> > > + * is operating as a root complex this needs to be switched to
> > > + * PCI_CLASS_BRIDGE_HOST or Linux will errantly try to process the BAR's on
> > > + * the device. Decoding setup is handled by the orion code.
> > > + */
> > >  static void rc_pci_fixup(struct pci_dev *dev)
> > >  {
> > > -	/*
> > > -	 * Prevent enumeration of root complex.
> > > -	 */
> > >  	if (dev->bus->parent == NULL && dev->devfn == 0) {
> > >  		int i;
> > >  
> > > +		dev->class &= 0xff;
> > > +		dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
> > >  		for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
> > >  			dev->resource[i].start = 0;
> > >  			dev->resource[i].end   = 0;
> > > diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c
> > > index 636d84b40466..9362b5fc116f 100644
> > > --- a/arch/arm/mach-mv78xx0/pcie.c
> > > +++ b/arch/arm/mach-mv78xx0/pcie.c
> > > @@ -177,14 +177,19 @@ static struct pci_ops pcie_ops = {
> > >  	.write = pcie_wr_conf,
> > >  };
> > >  
> > > +/*
> > > + * The root complex has a hardwired class of PCI_CLASS_MEMORY_OTHER, when it
> > > + * is operating as a root complex this needs to be switched to
> > > + * PCI_CLASS_BRIDGE_HOST or Linux will errantly try to process the BAR's on
> > > + * the device. Decoding setup is handled by the orion code.
> > > + */
> > >  static void rc_pci_fixup(struct pci_dev *dev)
> > >  {
> > > -	/*
> > > -	 * Prevent enumeration of root complex.
> > > -	 */
> > >  	if (dev->bus->parent == NULL && dev->devfn == 0) {
> > >  		int i;
> > >  
> > > +		dev->class &= 0xff;
> > > +		dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
> > >  		for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
> > >  			dev->resource[i].start = 0;
> > >  			dev->resource[i].end   = 0;
> > > diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
> > > index e94a61901ffd..7189a5b1ec46 100644
> > > --- a/arch/arm/mach-orion5x/Kconfig
> > > +++ b/arch/arm/mach-orion5x/Kconfig
> > > @@ -6,6 +6,7 @@ menuconfig ARCH_ORION5X
> > >  	select GPIOLIB
> > >  	select MVEBU_MBUS
> > >  	select FORCE_PCI
> > > +	select PCI_QUIRKS
> > >  	select PHYLIB if NETDEVICES
> > >  	select PLAT_ORION_LEGACY
> > >  	help
> > > diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
> > > index 76951bfbacf5..5145fe89702e 100644
> > > --- a/arch/arm/mach-orion5x/pci.c
> > > +++ b/arch/arm/mach-orion5x/pci.c
> > > @@ -509,14 +509,20 @@ static int __init pci_setup(struct pci_sys_data *sys)
> > >  /*****************************************************************************
> > >   * General PCIe + PCI
> > >   ****************************************************************************/
> > > +
> > > +/*
> > > + * The root complex has a hardwired class of PCI_CLASS_MEMORY_OTHER, when it
> > > + * is operating as a root complex this needs to be switched to
> > > + * PCI_CLASS_BRIDGE_HOST or Linux will errantly try to process the BAR's on
> > > + * the device. Decoding setup is handled by the orion code.
> > > + */
> > >  static void rc_pci_fixup(struct pci_dev *dev)
> > >  {
> > > -	/*
> > > -	 * Prevent enumeration of root complex.
> > > -	 */
> > >  	if (dev->bus->parent == NULL && dev->devfn == 0) {
> > >  		int i;
> > >  
> > > +		dev->class &= 0xff;
> > > +		dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
> > >  		for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
> > >  			dev->resource[i].start = 0;
> > >  			dev->resource[i].end   = 0;
> > > -- 
> > > 2.20.1
> > > 