[PATCH 07/11] dt-bindings: spi: spi-nxp-fspi: add a new property nxp,fspi-dll-slvdly

[Bough Chen]

> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
> Sent: 2022年7月5日 17:48
> To: Bough Chen <haibo.chen at nxp.com>; ashish.kumar at nxp.com;
> yogeshgaur.83 at gmail.com; broonie at kernel.org; robh+dt at kernel.org;
> krzysztof.kozlowski+dt at linaro.org; Han Xu <han.xu at nxp.com>;
> singh.kuldeep87k at gmail.com; tudor.ambarus at microchip.com;
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> richard at nod.at; vigneshr at ti.com; shawnguo at kernel.org;
> s.hauer at pengutronix.de; kernel at pengutronix.de
> Cc: linux-spi at vger.kernel.org; linux-kernel at vger.kernel.org;
> devicetree at vger.kernel.org; linux-mtd at lists.infradead.org;
> festevam at gmail.com; dl-linux-imx <linux-imx at nxp.com>;
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> Subject: Re: [PATCH 07/11] dt-bindings: spi: spi-nxp-fspi: add a new property
> nxp,fspi-dll-slvdly
> 
> On 05/07/2022 11:11, haibo.chen at nxp.com wrote:
> > From: Haibo Chen <haibo.chen at nxp.com>
> >
> > Add one optional property nxp,fspi-dll-slvdly
> >
> > Signed-off-by: Haibo Chen <haibo.chen at nxp.com>
> > ---
> >  Documentation/devicetree/bindings/spi/spi-nxp-fspi.yaml | 6 ++++++
> >  1 file changed, 6 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/spi/spi-nxp-fspi.yaml
> b/Documentation/devicetree/bindings/spi/spi-nxp-fspi.yaml
> > index 1b552c298277..6bd61565686a 100644
> > --- a/Documentation/devicetree/bindings/spi/spi-nxp-fspi.yaml
> > +++ b/Documentation/devicetree/bindings/spi/spi-nxp-fspi.yaml
> > @@ -45,6 +45,12 @@ properties:
> >        - const: fspi_en
> >        - const: fspi
> >
> > +  nxp,fspi-dll-slvdly:
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    description: |
> > +      Specify the DLL slave line delay value.
> 
> What are the units?

Do you mean here need to give more detail explain about this properity?

How about change like this?
   Specify the DLL slave line delay value. The delay target for slave delay line is: ((nxp,fspi-dll-slvdly+1) * 1/32 * clock cycle of reference clock (serial root clock). The range of this value is 0~16.


Best Regards
Haibo Chen

> 
> Best regards,
> Krzysztof