[PATCH 07/11] arm64: dts: mediatek: cherry: Enable I2C and SPI controllers

[Nícolas F. R. A. Prado]

On Thu, Jun 30, 2022 at 05:33:12PM +0200, AngeloGioacchino Del Regno wrote:
> This platform uses eight I2C controllers and one SPI controller:
> in preparation for enabling devices attached to these controllers,
> add basic configuration to enable the busses.
> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
> ---
>  .../boot/dts/mediatek/mt8195-cherry.dtsi      | 150 ++++++++++++++++++
>  1 file changed, 150 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> index 2f70341bba91..23a86d07274c 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> @@ -9,6 +9,13 @@
>  
>  / {
>  	aliases {
> +		i2c0 = &i2c0;
> +		i2c1 = &i2c1;
> +		i2c2 = &i2c2;
> +		i2c3 = &i2c3;
> +		i2c4 = &i2c4;
> +		i2c5 = &i2c5;
> +		i2c7 = &i2c7;
>  		mmc0 = &mmc0;
>  		serial0 = &uart0;
>  	};
> @@ -88,6 +95,65 @@ ppvar_sys: regulator-ppvar-sys {
>  	};
>  };
>  
> +&i2c0 {
> +	status = "okay";
> +
> +	clock-frequency = <400000>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&i2c0_pin>;

Very nitpicky: you could name it "i2c0_pins" to be consistent with the others
(including SPI on this patch).

> +};
[..]
> +&i2c7 {
> +	#address-cells = <1>;
> +	#size-cells = <0>;

These *-cells are already defined in the parent dtsi, so drop.

Reviewed-by: Nícolas F. R. A. Prado <nfraprado at collabora.com>

Thanks,
Nícolas