[bootwrapper PATCH v3 01/15] aarch64: correct ZCR_EL3.LEN initialization

[Andre Przywara]

On Tue, 25 Jan 2022 15:00:43 +0000
Mark Rutland <mark.rutland at arm.com> wrote:

> The ZCR_ELx.LEN field covers bits[3:0] of ZCR_ELx, and bits[8:4] are
> RAZ/WI, likely so that in future these can be used to extend LEN without
> complicating the probing of the maximum available vector length.
> 
> Currently ZCR_EL3_LEN_MASK is defined as 0x1ff, covering both the LEN
> field and the RAZ/WI bits.
> 
> To match the architecture as documented, reduce this down to 0xf, only
> covering the bits currently allocated to the LEN field. We can extend
> this in future if the LEN field is widened.
> 
> As the same time, rename ZCR_EL3_LEN_MASK to ZCR_EL3_LEN_MAX, as it is
> used as a value rather than as a bit mask.
> 
> Signed-off-by: Mark Rutland <mark.rutland at arm.com>
> Cc: Andre Przywara <andre.przywara at arm.com>
> Cc: Mark Brown <broonie at kernel.org>

Looks good to me:

Reviewed-by: Andre Przywara <andre.przywara at arm.com>

Cheers,
Andre

> ---
>  arch/aarch64/boot.S            | 2 +-
>  arch/aarch64/include/asm/cpu.h | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S
> index 72c6b79..ee9ddaa 100644
> --- a/arch/aarch64/boot.S
> +++ b/arch/aarch64/boot.S
> @@ -123,7 +123,7 @@ ASM_FUNC(_start)
>  	msr	cptr_el3, x0
>  	isb
>  
> -	mov	x0, #ZCR_EL3_LEN_MASK		// SVE: Enable full vector len
> +	mov	x0, #ZCR_EL3_LEN_MAX		// SVE: Enable full vector len
>  	msr	ZCR_EL3, x0			// for EL2.
>  
>  1:
> diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h
> index 63eb1c3..e3269b8 100644
> --- a/arch/aarch64/include/asm/cpu.h
> +++ b/arch/aarch64/include/asm/cpu.h
> @@ -30,7 +30,7 @@
>  #define CPTR_EL3_EZ		(1 << 8)
>  
>  #define ZCR_EL3			s3_6_c1_c2_0
> -#define ZCR_EL3_LEN_MASK	0x1ff
> +#define ZCR_EL3_LEN_MAX		0xf
>  
>  #define SCTLR_EL1_CP15BEN	(1 << 5)
>  #define SCTLR_EL1_RES1		(3 << 28 | 3 << 22 | 1 << 11)