[PATCH 6/8] x86: Add hardware prefetch control support for x86
Kohei Tarumizu
tarumizu.kohei at fujitsu.com
Mon Jan 24 23:14:12 PST 2022
This adds module init/exit code, and creates sysfs attribute file
"prefetch_control" for x86. This driver works only if the model is
INTEL_FAM6_BROADWELL_X at this point.
If you would like to support a new model with the same register
specifications as INTEL_FAM6_BROADWELL_X, it is possible to add the
model settings to array of broadwell_cpu_ids[].
The details of the registers to be read and written in this patch are
described below:
"https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html"
Volume 4
Signed-off-by: Kohei Tarumizu <tarumizu.kohei at fujitsu.com>
---
arch/x86/kernel/cpu/pfctl.c | 292 ++++++++++++++++++++++++++++++++++++
1 file changed, 292 insertions(+)
create mode 100644 arch/x86/kernel/cpu/pfctl.c
diff --git a/arch/x86/kernel/cpu/pfctl.c b/arch/x86/kernel/cpu/pfctl.c
new file mode 100644
index 000000000000..02628f6d2c05
--- /dev/null
+++ b/arch/x86/kernel/cpu/pfctl.c
@@ -0,0 +1,292 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 FUJITSU LIMITED
+ *
+ * x86 Hardware Prefetch Control support
+ */
+
+#include <linux/bitfield.h>
+#include <linux/cacheinfo.h>
+#include <linux/pfctl.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <asm/cpu_device_id.h>
+#include <asm/intel-family.h>
+#include <asm/msr.h>
+
+struct pfctl_driver x86_pfctl_driver;
+
+/**************************************
+ * Intle BROADWELL support
+ **************************************/
+
+/*
+ * The register specification for each bits of Intel BROADWELL is as
+ * follow:
+ *
+ * [0] L2 Hardware Prefetcher Disable (R/W)
+ * [1] L2 Adjacent Cache Line Prefetcher Disable (R/W)
+ * [2] DCU Hardware Prefetcher Disable (R/W)
+ * [3] DCU IP Prefetcher Disable (R/W)
+ * [63:4] Reserved
+ *
+ * See "Intel 64 and IA-32 Architectures Software Developer's Manual"
+ * (https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html)
+ * for register specification details.
+ */
+#define BROADWELL_L2_HWPF_FIELD BIT_ULL(0)
+#define BROADWELL_L2_ACLPF_FIELD BIT_ULL(1)
+#define BROADWELL_DCU_HWPF_FIELD BIT_ULL(2)
+#define BROADWELL_DCU_IPPF_FIELD BIT_ULL(3)
+
+static int broadwell_get_hwpf_enable(u64 reg, unsigned int level)
+{
+ switch (level) {
+ case 1:
+ return FIELD_GET(BROADWELL_DCU_HWPF_FIELD, reg);
+ case 2:
+ return FIELD_GET(BROADWELL_L2_HWPF_FIELD, reg);
+ default:
+ return -EINVAL;
+ }
+}
+
+static int broadwell_modify_hwpf_enable(u64 *reg, unsigned int level,
+ unsigned int val)
+{
+ switch (level) {
+ case 1:
+ *reg &= ~BROADWELL_DCU_HWPF_FIELD;
+ *reg |= FIELD_PREP(BROADWELL_DCU_HWPF_FIELD, val);
+ break;
+ case 2:
+ *reg &= ~BROADWELL_L2_HWPF_FIELD;
+ *reg |= FIELD_PREP(BROADWELL_L2_HWPF_FIELD, val);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int broadwell_get_ippf_enable(u64 reg, unsigned int level)
+{
+ switch (level) {
+ case 1:
+ return FIELD_GET(BROADWELL_DCU_IPPF_FIELD, reg);
+ default:
+ return -EINVAL;
+ }
+}
+
+static int broadwell_modify_ippf_enable(u64 *reg, unsigned int level,
+ unsigned int val)
+{
+ switch (level) {
+ case 1:
+ *reg &= ~BROADWELL_DCU_IPPF_FIELD;
+ *reg |= FIELD_PREP(BROADWELL_DCU_IPPF_FIELD, val);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int broadwell_get_aclpf_enable(u64 reg, unsigned int level)
+{
+ switch (level) {
+ case 2:
+ return FIELD_GET(BROADWELL_L2_ACLPF_FIELD, reg);
+ default:
+ return -EINVAL;
+ }
+}
+
+static int broadwell_modify_aclpf_enable(u64 *reg, unsigned int level,
+ unsigned int val)
+{
+ switch (level) {
+ case 2:
+ *reg &= ~BROADWELL_L2_ACLPF_FIELD;
+ *reg |= FIELD_PREP(BROADWELL_L2_ACLPF_FIELD, val);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int _broadwell_get_pfctl_params(struct prefetcher_options *opts, u64 reg,
+ unsigned int level, int supported_prefetcher)
+{
+ int ret;
+
+ if (supported_prefetcher & HWPF) {
+ ret = broadwell_get_hwpf_enable(reg, level);
+ if (ret < 0)
+ return ret;
+ opts->hwpf_enable = ret;
+ }
+
+ if (supported_prefetcher & IPPF) {
+ ret = broadwell_get_ippf_enable(reg, level);
+ if (ret < 0)
+ return ret;
+ opts->ippf_enable = ret;
+ }
+
+ if (supported_prefetcher & ACLPF) {
+ ret = broadwell_get_aclpf_enable(reg, level);
+ if (ret < 0)
+ return ret;
+ opts->aclpf_enable = ret;
+ }
+
+ return 0;
+}
+
+static int broadwell_get_pfctl_params(struct prefetcher_options *opts, u64 reg,
+ unsigned int level)
+{
+ int ret, supported_prefetcher;
+
+ if (level == 1)
+ supported_prefetcher =
+ x86_pfctl_driver.supported_l1d_prefetcher;
+ else if (level == 2)
+ supported_prefetcher =
+ x86_pfctl_driver.supported_l2_prefetcher;
+ else
+ return -EINVAL;
+
+ ret = _broadwell_get_pfctl_params(opts, reg, level, supported_prefetcher);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static int broadwell_modify_pfreg(u64 *reg, struct prefetcher_options *opts,
+ unsigned int level)
+{
+ int ret;
+
+ if (opts->hwpf_enable != PFCTL_PARAM_UNSET) {
+ ret = broadwell_modify_hwpf_enable(reg, level,
+ opts->hwpf_enable);
+ if (ret < 0)
+ return ret;
+ }
+
+ if (opts->ippf_enable != PFCTL_PARAM_UNSET) {
+ ret = broadwell_modify_ippf_enable(reg, level,
+ opts->ippf_enable);
+ if (ret < 0)
+ return ret;
+ }
+
+ if (opts->aclpf_enable != PFCTL_PARAM_UNSET) {
+ ret = broadwell_modify_aclpf_enable(reg, level,
+ opts->aclpf_enable);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int broadwell_read_pfreg(unsigned int cpu, unsigned int level,
+ struct prefetcher_options *opts)
+{
+ int ret;
+ u64 reg;
+
+ ret = rdmsrl_on_cpu(cpu, MSR_MISC_FEATURE_CONTROL, ®);
+ if (ret)
+ return ret;
+
+ ret = broadwell_get_pfctl_params(opts, reg, level);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int broadwell_write_pfreg(unsigned int cpu, unsigned int level,
+ struct prefetcher_options *opts)
+{
+ int ret;
+ u64 reg;
+
+ ret = rdmsrl_on_cpu(cpu, MSR_MISC_FEATURE_CONTROL, ®);
+ if (ret)
+ return ret;
+
+ ret = broadwell_modify_pfreg(®, opts, level);
+ if (ret < 0)
+ return ret;
+
+ ret = wrmsrl_on_cpu(cpu, MSR_MISC_FEATURE_CONTROL, reg);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+/*
+ * In addition to BROADWELL_X, NEHALEM and others have same register
+ * specifications as those represented by BROADWELL_XXX_FIELD.
+ * If you want to add support for these processor, add the new target model
+ * here.
+ */
+static const struct x86_cpu_id broadwell_cpu_ids[] = {
+ X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, NULL),
+ {}
+};
+
+/***** end of Intel BROADWELL support *****/
+
+static int __init setup_pfctl_driver_params(void)
+{
+ if (x86_match_cpu(broadwell_cpu_ids)) {
+ x86_pfctl_driver.supported_l1d_prefetcher = HWPF|IPPF;
+ x86_pfctl_driver.supported_l2_prefetcher = HWPF|ACLPF;
+ x86_pfctl_driver.read_pfreg = broadwell_read_pfreg;
+ x86_pfctl_driver.write_pfreg = broadwell_write_pfreg;
+ } else {
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static int __init x86_pfctl_init(void)
+{
+ int ret;
+
+ ret = setup_pfctl_driver_params();
+ if (ret < 0)
+ return ret;
+
+ ret = pfctl_register_driver(&x86_pfctl_driver);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static void __exit x86_pfctl_exit(void)
+{
+ pfctl_unregister_driver(&x86_pfctl_driver);
+}
+
+late_initcall(x86_pfctl_init);
+module_exit(x86_pfctl_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("FUJITSU LIMITED");
+MODULE_DESCRIPTION("x86 Hardware Prefetch Control Driver");
--
2.27.0
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