[bootwrapper PATCH v2 06/13] aarch64: initialize SCTLR_ELx for the boot-wrapper

[Mark Rutland]

On Mon, Jan 17, 2022 at 12:15:57PM +0000, Mark Rutland wrote:
> On Fri, Jan 14, 2022 at 06:12:47PM +0000, Andre Przywara wrote:
> > On Fri, 14 Jan 2022 10:56:46 +0000
> > Mark Rutland <mark.rutland at arm.com> wrote:

> > > +
> > > +#define SCTLR_EL1_RES1		(BIT(29) | BIT(28) | BIT(23) | BIT(22) | \
> > > +				 BIT(11) | BIT(8) | BIT(7) | BIT(4))
> > 
> > - The kernel sets TSCXT(bit[20]), and the ARM ARM says that the value
> > should be RES1 if FEAT_CSV2_* is not implemented. Should we copy this?
> 
> Yes, we should. I'll go and fold that in.
> 
> > - The kernel clears ITD(bit[7]), and the ARM ARM says it's *Otherwise* RES1
> > (no AArch32 in EL0). I feel like we should not disable IT instructions in
> > EL0 needlessly?
> 
> Per the ARM ARM the bit resets to an UNKNOWN value, and so per our usual
> policy the kernel must initialize that before it can depend upon it, and
> IIUC you say the kernel already does so.
> 
> So it shouldn't matter what the boot-wrapper does, and for consitency, I
> think the boot-wrapper should set this to 0b1.
> 
> > - I also feel like we should set CP15BEN(bit[5]), for similar reasons.
> 
> I agree.

I thought you meant it was also RES1 in the same case as ITD. It's actually
RES0 when there's no AArch32 EL0 support, so I'm not going to add it to
SCTLR_EL1_RES1.

I have added TSCXT (bit[20]) and ITD (bit[7]), as above, as those are RES1 in
some contexts.

THanks,
Mark.