[v10,2/3] drm/mediatek: implement the DSI HS packets aligned

[AngeloGioacchino Del Regno]

Il 19/01/22 09:35, Andrzej Hajda ha scritto:
> 
> On 19.01.2022 03:25, Rex-BC Chen wrote:
>> Some DSI RX devices (for example, anx7625) require last alignment of
>> packets on all lanes after each row of data is sent.
>> Otherwise, there will be some issues of shift or scroll for screen.
>>
>> Take horizontal_sync_active_byte for a example,
>> we roundup the HSA packet data to lane number, and the subtraction of 2
>> is the packet data value added by the roundup operation, making the
>> long packets are integer multiples of lane number.
>> This value (2) varies with the lane number, and that is the reason we
>> do this operation when the lane number is 4.
>>
>> In the previous operation of function "mtk_dsi_config_vdo_timing",
>> the length of HSA and HFP data packets has been adjusted to an
>> integration multiple of lane number.
>> Since the number of RGB data packets cannot be guaranteed to be an
>> integer multiple of lane number, we modify the data packet length of
>> HBP so that the number of HBP + RGB is equal to the lane number.
>> So after sending a line of data (HSA + HBP + RGB + HFP), the data
>> lanes are aligned.
>>
>> Signed-off-by: Jitao Shi <jitao.shi at mediatek.com>
>> Signed-off-by: Rex-BC Chen <rex-bc.chen at mediatek.com>
>> Signed-off-by: Xinlei Lee <xinlei.lee at mediatek.com>
> 
> Reviewed-by: Andrzej Hajda <andrzej.hajda at intel.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>

> 
> Regards
> 
> Andrzej
> 
>> ---
>>   drivers/gpu/drm/mediatek/mtk_dsi.c | 12 ++++++++++++
>>   1 file changed, 12 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
>> index 5d90d2eb0019..e91b3fff4342 100644
>> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
>> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
>> @@ -500,6 +500,18 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
>>           DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n");
>>       }
>> +    if ((dsi->mode_flags & MIPI_DSI_HS_PKT_END_ALIGNED) &&
>> +        (dsi->lanes == 4)) {
>> +        horizontal_sync_active_byte =
>> +            roundup(horizontal_sync_active_byte, dsi->lanes) - 2;
>> +        horizontal_frontporch_byte =
>> +            roundup(horizontal_frontporch_byte, dsi->lanes) - 2;
>> +        horizontal_backporch_byte =
>> +            roundup(horizontal_backporch_byte, dsi->lanes) - 2;
>> +        horizontal_backporch_byte -=
>> +            (vm->hactive * dsi_tmp_buf_bpp + 2) % dsi->lanes;
>> +    }
>> +
>>       writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
>>       writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
>>       writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);