[PATCH net v3 0/9] Xilinx axienet fixes
Robert Hancock
robert.hancock at calian.com
Tue Jan 18 13:41:23 PST 2022
Various fixes for the Xilinx AXI Ethernet driver.
Changed since v2:
-added Reviewed-by tags, added some explanation to commit
messages, no code changes
Changed since v1:
-corrected a Fixes tag to point to mainline commit
-split up reset changes into 3 patches
-added ratelimit on netdev_warn in TX busy case
Robert Hancock (9):
net: axienet: increase reset timeout
net: axienet: Wait for PhyRstCmplt after core reset
net: axienet: reset core on initialization prior to MDIO access
net: axienet: add missing memory barriers
net: axienet: limit minimum TX ring size
net: axienet: Fix TX ring slot available check
net: axienet: fix number of TX ring slots for available check
net: axienet: fix for TX busy handling
net: axienet: increase default TX ring size to 128
.../net/ethernet/xilinx/xilinx_axienet_main.c | 135 +++++++++++-------
1 file changed, 84 insertions(+), 51 deletions(-)
--
2.31.1
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