[PATCH net v2 0/9] Xilinx axienet fixes

[Robert Hancock]

On Tue, 2022-01-18 at 13:00 -0800, Jakub Kicinski wrote:
> On Tue, 18 Jan 2022 20:45:31 +0000 Robert Hancock wrote:
> > On Wed, 2022-01-12 at 11:36 -0600, Robert Hancock wrote:
> > > Various fixes for the Xilinx AXI Ethernet driver.
> > > 
> > > Changed since v1:
> > > -corrected a Fixes tag to point to mainline commit
> > > -split up reset changes into 3 patches
> > > -added ratelimit on netdev_warn in TX busy case
> > > 
> > > Robert Hancock (9):
> > >   net: axienet: increase reset timeout
> > >   net: axienet: Wait for PhyRstCmplt after core reset
> > >   net: axienet: reset core on initialization prior to MDIO access
> > >   net: axienet: add missing memory barriers
> > >   net: axienet: limit minimum TX ring size
> > >   net: axienet: Fix TX ring slot available check
> > >   net: axienet: fix number of TX ring slots for available check
> > >   net: axienet: fix for TX busy handling
> > >   net: axienet: increase default TX ring size to 128
> > 
> > Any other comments/reviews on this patch set? It's marked as Changes
> > Requested
> > in Patchwork, but I don't think I saw any discussions that ended up with
> > any
> > changes being asked for?
> 
> Perhaps it was done in anticipation to follow up to Radhey's or
> Andrew's question but seems like you answered those. Or maybe because
> of the missing CC on of hancock at sedsystems.ca on patch 5?

That's actually my old email address (before the renaming from SED Systems to
Calian AT). I think get_maintainer.pl picks that up as I had some past commits
to the driver with that email.

> Not sure.
> 
> Could you fold some of the explanations into commit messages, add
> Andrew's Acks and post a v3? 
> 
> We could probably apply as is but since it was marked as Changes
> Requested I can't be sure someone hasn't stopped reviewing in
> anticipation of v3.

Can do.

> 
> Thanks!
-- 
Robert Hancock
Senior Hardware Designer, Calian Advanced Technologies
www.calian.com