[PATCH net v2 2/9] net: axienet: Wait for PhyRstCmplt after core reset

[Radhey Shyam Pandey]

> -----Original Message-----
> From: Robert Hancock <robert.hancock at calian.com>
> Sent: Wednesday, January 12, 2022 11:07 PM
> To: netdev at vger.kernel.org
> Cc: Radhey Shyam Pandey <radheys at xilinx.com>; davem at davemloft.net;
> kuba at kernel.org; linux-arm-kernel at lists.infradead.org; Michal Simek
> <michals at xilinx.com>; ariane.keller at tik.ee.ethz.ch; daniel at iogearbox.net;
> Robert Hancock <robert.hancock at calian.com>
> Subject: [PATCH net v2 2/9] net: axienet: Wait for PhyRstCmplt after core reset
> 
> When resetting the device, wait for the PhyRstCmplt bit to be set
> in the interrupt status register before continuing initialization, to
> ensure that the core is actually ready. The MgtRdy bit could also be
> waited for, but unfortunately when using 7-series devices, the bit does

Just to understand - can you share 7- series design details.
Based on documentation - This MgtRdy bit indicates if the TEMAC core is
out of reset and ready for use. In systems that use an serial transceiver, 
this bit goes to 1 when the serial transceiver is ready to use.

Also if we don't wait for phy reset - what is the issue we are seeing?

> not appear to work as documented (it seems to behave as some sort of
> link state indication and not just an indication the transceiver is
> ready) so it can't really be relied on.
> 
> Fixes: 8a3b7a252dca9 ("drivers/net/ethernet/xilinx: added Xilinx AXI Ethernet
> driver")
> Signed-off-by: Robert Hancock <robert.hancock at calian.com>
> ---
>  drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> index f950342f6467..f425a8404a9b 100644
> --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> @@ -516,6 +516,16 @@ static int __axienet_device_reset(struct axienet_local
> *lp)
>  		return ret;
>  	}
> 
> +	/* Wait for PhyRstCmplt bit to be set, indicating the PHY reset has
> finished */
> +	ret = read_poll_timeout(axienet_ior, value,
> +				value & XAE_INT_PHYRSTCMPLT_MASK,
> +				DELAY_OF_ONE_MILLISEC, 50000, false, lp,
> +				XAE_IS_OFFSET);
> +	if (ret) {
> +		dev_err(lp->dev, "%s: timeout waiting for PhyRstCmplt\n",
> __func__);
> +		return ret;
> +	}
> +
>  	return 0;
>  }
> 
> --
> 2.31.1