[PATCH 3/3] PCI: aardvark: Implement emulated root PCI bridge
Bjorn Helgaas
helgaas at kernel.org
Fri Jan 7 15:17:34 PST 2022
[+cc Pali; sorry, I meant to cc you on this but forgot]
On Fri, Jan 07, 2022 at 03:27:38PM -0600, Bjorn Helgaas wrote:
> On Fri, Jun 29, 2018 at 11:22:31AM +0200, Thomas Petazzoni wrote:
>
> > +static void advk_sw_pci_bridge_init(struct advk_pcie *pcie)
> > +{
> > + struct pci_sw_bridge *bridge = &pcie->bridge;
>
> > + /* Support interrupt A for MSI feature */
> > + bridge->conf.intpin = PCIE_CORE_INT_A_ASSERT_ENABLE;
>
> Only 3.5 years later, IIUC, this is the value you get when you read
> PCI_INTERRUPT_PIN, so I think this should be PCI_INTERRUPT_INTA, not
> PCIE_CORE_INT_A_ASSERT_ENABLE.
>
> Readers expect to get the values defined in the PCI spec, i.e.,
>
> PCI_INTERRUPT_UNKNOWN
> PCI_INTERRUPT_INTA
> PCI_INTERRUPT_INTB
> PCI_INTERRUPT_INTC
> PCI_INTERRUPT_INTD
>
> Bjorn
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