net: phy: marvell: network working with generic PHY and not with marvell PHY

[Russell King (Oracle)]

On Tue, Jan 04, 2022 at 03:46:19PM +0100, Andrew Lunn wrote:
> > @@ -1227,16 +1227,18 @@ static int m88e1118_config_init(struct phy_device *phydev)
> >  {
> >  	int err;
> >  
> > -	/* Change address */
> > -	err = marvell_set_page(phydev, MII_MARVELL_MSCR_PAGE);
> > -	if (err < 0)
> > -		return err;
> > -
> >  	/* Enable 1000 Mbit */
> > -	err = phy_write(phydev, 0x15, 0x1070);
> > +	err = phy_write_paged(phydev, MII_MARVELL_MSCR_PAGE,
> > +			      MII_88E1121_PHY_MSCR_REG, 0x1070);
> 
> Ah, yes, keeping this makes it more backwards compatible.
> 
> It would be nice to replace the 0x1070 with #defines.
> 
> We already have:
> 
> #define MII_88E1121_PHY_MSCR_RX_DELAY	BIT(5)
> #define MII_88E1121_PHY_MSCR_TX_DELAY	BIT(4)
> #define MII_88E1121_PHY_MSCR_DELAY_MASK	(BIT(5) | BIT(4))
> 
> Bits 6 is the MSB of the default MAC speed.
> Bit 13 is the LSB of the default MAC speed. These two should default to 10b = 1000Mbps
> Bit 12 is reserved, and should be written 1.

Hmm, seems odd that these speed bits match BMCR, and I'm not sure why
the default MAC speed would have any bearing on whether gigabit mode
is enabled. If they default to 10b, then the write should have no effect
unless boot firmware has changed them.

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