[PATCH v5 34/69] KVM: arm64: nv: Configure HCR_EL2 for nested virtualization

[Ganapatrao Kulkarni]

On 04-01-2022 03:09 pm, Marc Zyngier wrote:
> On Tue, 04 Jan 2022 08:53:42 +0000,
> Ganapatrao Kulkarni <gankulkarni at os.amperecomputing.com> wrote:
>>
>>
>>
>> On 30-11-2021 01:31 am, Marc Zyngier wrote:
>>> From: Jintack Lim <jintack.lim at linaro.org>
>>>
>>> We enable nested virtualization by setting the HCR NV and NV1 bit.
>>>
>>> When the virtual E2H bit is set, we can support EL2 register accesses
>>> via EL1 registers from the virtual EL2 by doing trap-and-emulate. A
>>> better alternative, however, is to allow the virtual EL2 to access EL2
>>> register states without trap. This can be easily achieved by not traping
>>> EL1 registers since those registers already have EL2 register states.
>>>
>>> Signed-off-by: Jintack Lim <jintack.lim at linaro.org>
>>> Signed-off-by: Marc Zyngier <maz at kernel.org>
>>> ---
>>>    arch/arm64/include/asm/kvm_arm.h |  1 +
>>>    arch/arm64/kvm/hyp/vhe/switch.c  | 38 +++++++++++++++++++++++++++++---
>>>    2 files changed, 36 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
>>> index 68af5509e4b0..b8a0d410035b 100644
>>> --- a/arch/arm64/include/asm/kvm_arm.h
>>> +++ b/arch/arm64/include/asm/kvm_arm.h
>>> @@ -87,6 +87,7 @@
>>>    			 HCR_BSU_IS | HCR_FB | HCR_TACR | \
>>>    			 HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW | HCR_TLOR | \
>>>    			 HCR_FMO | HCR_IMO | HCR_PTW )
>>> +#define HCR_GUEST_NV_FILTER_FLAGS (HCR_ATA | HCR_API | HCR_APK | HCR_RW)
>>>    #define HCR_VIRT_EXCP_MASK (HCR_VSE | HCR_VI | HCR_VF)
>>>    #define HCR_HOST_NVHE_FLAGS (HCR_RW | HCR_API | HCR_APK | HCR_ATA)
>>>    #define HCR_HOST_NVHE_PROTECTED_FLAGS (HCR_HOST_NVHE_FLAGS | HCR_TSC)
>>> diff --git a/arch/arm64/kvm/hyp/vhe/switch.c b/arch/arm64/kvm/hyp/vhe/switch.c
>>> index 57f43e607819..da80c969e623 100644
>>> --- a/arch/arm64/kvm/hyp/vhe/switch.c
>>> +++ b/arch/arm64/kvm/hyp/vhe/switch.c
>>> @@ -36,9 +36,41 @@ static void __activate_traps(struct kvm_vcpu *vcpu)
>>>    	u64 hcr = vcpu->arch.hcr_el2;
>>>    	u64 val;
>>>    -	/* Trap VM sysreg accesses if an EL2 guest is not using
>>> VHE. */
>>> -	if (vcpu_mode_el2(vcpu) && !vcpu_el2_e2h_is_set(vcpu))
>>> -		hcr |= HCR_TVM | HCR_TRVM;
>>> +	if (is_hyp_ctxt(vcpu)) {
>>> +		hcr |= HCR_NV;
>>> +
>>> +		if (!vcpu_el2_e2h_is_set(vcpu)) {
>>> +			/*
>>> +			 * For a guest hypervisor on v8.0, trap and emulate
>>> +			 * the EL1 virtual memory control register accesses.
>>> +			 */
>>> +			hcr |= HCR_TVM | HCR_TRVM | HCR_NV1;
>>> +		} else {
>>> +			/*
>>> +			 * For a guest hypervisor on v8.1 (VHE), allow to
>>> +			 * access the EL1 virtual memory control registers
>>> +			 * natively. These accesses are to access EL2 register
>>> +			 * states.
>>> +			 * Note that we still need to respect the virtual
>>> +			 * HCR_EL2 state.
>>> +			 */
>>> +			u64 vhcr_el2 = __vcpu_sys_reg(vcpu, HCR_EL2);
>>> +
>>> +			vhcr_el2 &= ~HCR_GUEST_NV_FILTER_FLAGS;
>>
>> Why HCR_RW is cleared here, May I know please?
> 
> Good question. That's clearly a leftover from an early rework. It
> really doesn't matter, as we are merging the guest's configuration
> into the host's, and the host already has HCR_EL2.RW set.

Thanks, I too felt the same.

x>
> What HCR_GUEST_NV_FILTER_FLAGS should contain is only the bits we
> don't want to deal with at this stage of the NV support. I'll fix that
> for the next round.
> 
sure, thanks.

> Thanks,
> 
> 	M.
> 

Thanks,
Ganapat