[PATCH v2] arm64: dts: rockchip: Add sata nodes to rk356x
Johan Jonker
jbx6244 at gmail.com
Sun Feb 27 01:32:51 PST 2022
Hi Frank,
Combine your patch in a serie with the ahci-platform.yaml conversion and
include all current CC people and Rockchip list.
Your conversion and DT patch contains lots of errors.
Check your serie before you submit and fix.
ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- make dt_binding_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/ata/ahci-platform.yaml
ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- make dtbs_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/ata/ahci-platform.yaml
Add power-domains as a new property after the conversion patch.
Johan
===
make a serie:
conversion ahci-platform.yaml
power-domains patch
rockchip rk356x sata nodes patch
On 2/27/22 09:21, Frank Wunderlich wrote:
> From: Frank Wunderlich <frank-w at public-files.de>
>
> RK356x supports up to 3 sata controllers which were compatible with the
> existing snps,dwc-ahci binding.
>
> Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
> ---
> changes in v2:
> - added sata0 + 1, but have only tested sata2
> ---
> arch/arm64/boot/dts/rockchip/rk356x.dtsi | 45 ++++++++++++++++++++++++
> 1 file changed, 45 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> index 7cdef800cb3c..2e2e73be7417 100644
> --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> @@ -230,6 +230,51 @@ scmi_shmem: sram at 0 {
> };
> };
>
> + sata0: sata at fc000000 {
rk3566 has no combphy0
Move to rk3568.dtsi
> + compatible = "snps,dwc-ahci";
> + reg = <0 0xfc000000 0 0x1000>;
> + clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>,
> + <&cru CLK_SATA0_RXOOB>;
> + clock-names = "sata", "pmalive", "rxoob";
remove
> + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hostc";
remove
> + phys = <&combphy0 PHY_TYPE_SATA>;
> + phy-names = "sata-phy";
> + ports-implemented = <0x1>;
> + power-domains = <&power RK3568_PD_PIPE>;
> + status = "disabled";
> + };
> +
> + sata1: sata at fc400000 {
> + compatible = "snps,dwc-ahci";
> + reg = <0 0xfc400000 0 0x1000>;
> + clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>,
> + <&cru CLK_SATA1_RXOOB>;
> + clock-names = "sata", "pmalive", "rxoob";
remove
> + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hostc";
remove
> + phys = <&combphy1 PHY_TYPE_SATA>;
> + phy-names = "sata-phy";
> + ports-implemented = <0x1>;
> + power-domains = <&power RK3568_PD_PIPE>;
> + status = "disabled";
> + };
> +
> + sata2: sata at fc800000 {
> + compatible = "snps,dwc-ahci";
> + reg = <0 0xfc800000 0 0x1000>;
> + clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>,
> + <&cru CLK_SATA2_RXOOB>;
> + clock-names = "sata", "pmalive", "rxoob";
remove
> + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hostc";
remove
> + phys = <&combphy2 PHY_TYPE_SATA>;
> + phy-names = "sata-phy";
> + ports-implemented = <0x1>;
> + power-domains = <&power RK3568_PD_PIPE>;
> + status = "disabled";
> + };
> +
> gic: interrupt-controller at fd400000 {
> compatible = "arm,gic-v3";
> reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
More information about the linux-arm-kernel
mailing list