[PATCH 1/4] dt-bindings: clock: Add imx93 clock support
Abel Vesa
abel.vesa at nxp.com
Mon Feb 21 03:55:54 PST 2022
On 22-02-15 16:18:32, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan at nxp.com>
>
> Add the clock dt-binding file for i.MX93.
>
> Signed-off-by: Peng Fan <peng.fan at nxp.com>
> ---
> .../bindings/clock/imx93-clock.yaml | 63 ++++++
> include/dt-bindings/clock/imx93-clock.h | 200 ++++++++++++++++++
> 2 files changed, 263 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/imx93-clock.yaml
> create mode 100644 include/dt-bindings/clock/imx93-clock.h
>
Put the documentation part in a separate patch please.
> diff --git a/Documentation/devicetree/bindings/clock/imx93-clock.yaml b/Documentation/devicetree/bindings/clock/imx93-clock.yaml
> new file mode 100644
> index 000000000000..a4c3ae23b8c3
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/imx93-clock.yaml
> @@ -0,0 +1,63 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/imx93-clock.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NXP i.MX93 Clock Control Module Binding
> +
> +maintainers:
> + - Peng Fan <peng.fan at nxp.com>
> +
> +description: |
> + i.MX93 clock control module is an integrated clock controller, which
> + includes clock generator, clock gate and supplies to all modules.
> +
> +properties:
> + compatible:
> + enum:
> + - fsl,imx93-ccm
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + description:
> + specify the external clocks used by the CCM module.
> + items:
> + - description: 32k osc
> + - description: 24m osc
> + - description: ext1 clock input
> +
> + clock-names:
> + description:
> + specify the external clocks names used by the CCM module.
> + items:
> + - const: osc_32k
> + - const: osc_24m
> + - const: clk_ext1
> +
> + '#clock-cells':
> + const: 1
> + description:
> + The clock consumer should specify the desired clock by having the clock
> + ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx93-clock.h
> + for the full list of i.MX93 clock IDs.
> +
> +required:
> + - compatible
> + - reg
> + - '#clock-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + # Clock Control Module node:
> + - |
> + clock-controller at 44450000 {
> + compatible = "fsl,imx93-ccm";
> + reg = <0x44450000 0x10000>;
> + #clock-cells = <1>;
> + };
> +
> +...
> diff --git a/include/dt-bindings/clock/imx93-clock.h b/include/dt-bindings/clock/imx93-clock.h
> new file mode 100644
> index 000000000000..416e6fd7856d
> --- /dev/null
> +++ b/include/dt-bindings/clock/imx93-clock.h
> @@ -0,0 +1,200 @@
> +/* SPDX-License-Identifier: GPL-2.0+ OR MIT */
> +/*
> + * Copyright 2021 NXP
> + */
> +
> +#ifndef __DT_BINDINGS_CLOCK_IMX93_CLK_H
> +#define __DT_BINDINGS_CLOCK_IMX93_CLK_H
> +
> +#define IMX93_CLK_DUMMY 0
> +#define IMX93_CLK_24M 1
> +#define IMX93_CLK_EXT1 2
> +#define IMX93_CLK_SYS_PLL_PFD0 3
> +#define IMX93_CLK_SYS_PLL_PFD0_DIV2 4
> +#define IMX93_CLK_SYS_PLL_PFD1 5
> +#define IMX93_CLK_SYS_PLL_PFD1_DIV2 6
> +#define IMX93_CLK_SYS_PLL_PFD2 7
> +#define IMX93_CLK_SYS_PLL_PFD2_DIV2 8
> +#define IMX93_CLK_AUDIO_PLL 9
> +#define IMX93_CLK_VIDEO_PLL 10
> +#define IMX93_CLK_A55_PERIPH 11
> +#define IMX93_CLK_A55_MTR_BUS 12
> +#define IMX93_CLK_A55 13
> +#define IMX93_CLK_M33 14
> +#define IMX93_CLK_BUS_WAKEUP 15
> +#define IMX93_CLK_BUS_AON 16
> +#define IMX93_CLK_WAKEUP_AXI 17
> +#define IMX93_CLK_SWO_TRACE 18
> +#define IMX93_CLK_M33_SYSTICK 19
> +#define IMX93_CLK_FLEXIO1 20
> +#define IMX93_CLK_FLEXIO2 21
> +#define IMX93_CLK_LPIT1 22
> +#define IMX93_CLK_LPIT2 23
> +#define IMX93_CLK_LPTMR1 24
> +#define IMX93_CLK_LPTMR2 25
> +#define IMX93_CLK_TPM1 26
> +#define IMX93_CLK_TPM2 27
> +#define IMX93_CLK_TPM3 28
> +#define IMX93_CLK_TPM4 29
> +#define IMX93_CLK_TPM5 30
> +#define IMX93_CLK_TPM6 31
> +#define IMX93_CLK_FLEXSPI1 32
> +#define IMX93_CLK_CAN1 33
> +#define IMX93_CLK_CAN2 34
> +#define IMX93_CLK_LPUART1 35
> +#define IMX93_CLK_LPUART2 36
> +#define IMX93_CLK_LPUART3 37
> +#define IMX93_CLK_LPUART4 38
> +#define IMX93_CLK_LPUART5 39
> +#define IMX93_CLK_LPUART6 40
> +#define IMX93_CLK_LPUART7 41
> +#define IMX93_CLK_LPUART8 42
> +#define IMX93_CLK_LPI2C1 43
> +#define IMX93_CLK_LPI2C2 44
> +#define IMX93_CLK_LPI2C3 45
> +#define IMX93_CLK_LPI2C4 46
> +#define IMX93_CLK_LPI2C5 47
> +#define IMX93_CLK_LPI2C6 48
> +#define IMX93_CLK_LPI2C7 49
> +#define IMX93_CLK_LPI2C8 50
> +#define IMX93_CLK_LPSPI1 51
> +#define IMX93_CLK_LPSPI2 52
> +#define IMX93_CLK_LPSPI3 53
> +#define IMX93_CLK_LPSPI4 54
> +#define IMX93_CLK_LPSPI5 55
> +#define IMX93_CLK_LPSPI6 56
> +#define IMX93_CLK_LPSPI7 57
> +#define IMX93_CLK_LPSPI8 58
> +#define IMX93_CLK_I3C1 59
> +#define IMX93_CLK_I3C2 60
> +#define IMX93_CLK_USDHC1 61
> +#define IMX93_CLK_USDHC2 62
> +#define IMX93_CLK_USDHC3 63
> +#define IMX93_CLK_SAI1 64
> +#define IMX93_CLK_SAI2 65
> +#define IMX93_CLK_SAI3 66
> +#define IMX93_CLK_CCM_CKO1 67
> +#define IMX93_CLK_CCM_CKO2 68
> +#define IMX93_CLK_CCM_CKO3 69
> +#define IMX93_CLK_CCM_CKO4 70
> +#define IMX93_CLK_HSIO 71
> +#define IMX93_CLK_HSIO_USB_TEST_60M 72
> +#define IMX93_CLK_HSIO_ACSCAN_80M 73
> +#define IMX93_CLK_HSIO_ACSCAN_480M 74
> +#define IMX93_CLK_ML_APB 75
> +#define IMX93_CLK_ML 76
> +#define IMX93_CLK_MEDIA_AXI 77
> +#define IMX93_CLK_MEDIA_APB 78
> +#define IMX93_CLK_MEDIA_LDB 79
> +#define IMX93_CLK_MEDIA_DISP_PIX 80
> +#define IMX93_CLK_CAM_PIX 81
> +#define IMX93_CLK_MIPI_TEST_BYTE 82
> +#define IMX93_CLK_MIPI_PHY_CFG 83
> +#define IMX93_CLK_ADC 84
> +#define IMX93_CLK_PDM 85
> +#define IMX93_CLK_TSTMR1 86
> +#define IMX93_CLK_TSTMR2 87
> +#define IMX93_CLK_MQS1 88
> +#define IMX93_CLK_MQS2 89
> +#define IMX93_CLK_AUDIO_XCVR 90
> +#define IMX93_CLK_SPDIF 91
> +#define IMX93_CLK_ENET 92
> +#define IMX93_CLK_ENET_TIMER1 93
> +#define IMX93_CLK_ENET_TIMER2 94
> +#define IMX93_CLK_ENET_REF 95
> +#define IMX93_CLK_ENET_REF_PHY 96
> +#define IMX93_CLK_I3C1_SLOW 97
> +#define IMX93_CLK_I3C2_SLOW 98
> +#define IMX93_CLK_USB_PHY_BURUNIN 99
> +#define IMX93_CLK_PAL_CAME_SCAN 100
> +#define IMX93_CLK_A55_GATE 101
> +#define IMX93_CLK_CM33_GATE 102
> +#define IMX93_CLK_ADC1_GATE 103
> +#define IMX93_CLK_WDOG1_GATE 104
> +#define IMX93_CLK_WDOG2_GATE 105
> +#define IMX93_CLK_WDOG3_GATE 106
> +#define IMX93_CLK_WDOG4_GATE 107
> +#define IMX93_CLK_WDOG5_GATE 108
> +#define IMX93_CLK_SEMA1_GATE 109
> +#define IMX93_CLK_SEMA2_GATE 110
> +#define IMX93_CLK_MU_A_GATE 111
> +#define IMX93_CLK_MU_B_GATE 112
> +#define IMX93_CLK_EDMA1_GATE 113
> +#define IMX93_CLK_EDMA2_GATE 114
> +#define IMX93_CLK_FLEXSPI1_GATE 115
> +#define IMX93_CLK_GPIO1_GATE 116
> +#define IMX93_CLK_GPIO2_GATE 117
> +#define IMX93_CLK_GPIO3_GATE 118
> +#define IMX93_CLK_GPIO4_GATE 119
> +#define IMX93_CLK_FLEXIO1_GATE 120
> +#define IMX93_CLK_FLEXIO2_GATE 121
> +#define IMX93_CLK_LPIT1_GATE 122
> +#define IMX93_CLK_LPIT2_GATE 123
> +#define IMX93_CLK_LPTMR1_GATE 124
> +#define IMX93_CLK_LPTMR2_GATE 125
> +#define IMX93_CLK_TPM1_GATE 126
> +#define IMX93_CLK_TPM2_GATE 127
> +#define IMX93_CLK_TPM3_GATE 128
> +#define IMX93_CLK_TPM4_GATE 129
> +#define IMX93_CLK_TPM5_GATE 130
> +#define IMX93_CLK_TPM6_GATE 131
> +#define IMX93_CLK_CAN1_GATE 132
> +#define IMX93_CLK_CAN2_GATE 133
> +#define IMX93_CLK_LPUART1_GATE 134
> +#define IMX93_CLK_LPUART2_GATE 135
> +#define IMX93_CLK_LPUART3_GATE 136
> +#define IMX93_CLK_LPUART4_GATE 137
> +#define IMX93_CLK_LPUART5_GATE 138
> +#define IMX93_CLK_LPUART6_GATE 139
> +#define IMX93_CLK_LPUART7_GATE 140
> +#define IMX93_CLK_LPUART8_GATE 141
> +#define IMX93_CLK_LPI2C1_GATE 142
> +#define IMX93_CLK_LPI2C2_GATE 143
> +#define IMX93_CLK_LPI2C3_GATE 144
> +#define IMX93_CLK_LPI2C4_GATE 145
> +#define IMX93_CLK_LPI2C5_GATE 146
> +#define IMX93_CLK_LPI2C6_GATE 147
> +#define IMX93_CLK_LPI2C7_GATE 148
> +#define IMX93_CLK_LPI2C8_GATE 149
> +#define IMX93_CLK_LPSPI1_GATE 150
> +#define IMX93_CLK_LPSPI2_GATE 151
> +#define IMX93_CLK_LPSPI3_GATE 152
> +#define IMX93_CLK_LPSPI4_GATE 153
> +#define IMX93_CLK_LPSPI5_GATE 154
> +#define IMX93_CLK_LPSPI6_GATE 155
> +#define IMX93_CLK_LPSPI7_GATE 156
> +#define IMX93_CLK_LPSPI8_GATE 157
> +#define IMX93_CLK_I3C1_GATE 158
> +#define IMX93_CLK_I3C2_GATE 159
> +#define IMX93_CLK_USDHC1_GATE 160
> +#define IMX93_CLK_USDHC2_GATE 161
> +#define IMX93_CLK_USDHC3_GATE 162
> +#define IMX93_CLK_SAI1_GATE 163
> +#define IMX93_CLK_SAI2_GATE 164
> +#define IMX93_CLK_SAI3_GATE 165
> +#define IMX93_CLK_MIPI_CSI_GATE 166
> +#define IMX93_CLK_MIPI_DSI_GATE 167
> +#define IMX93_CLK_LVDS_GATE 168
> +#define IMX93_CLK_LCDIF_GATE 169
> +#define IMX93_CLK_PXP_GATE 170
> +#define IMX93_CLK_ISI_GATE 171
> +#define IMX93_CLK_NIC_MEDIA_GATE 172
> +#define IMX93_CLK_USB_CONTROLLER_GATE 173
> +#define IMX93_CLK_USB_TEST_60M_GATE 174
> +#define IMX93_CLK_HSIO_TROUT_24M_GATE 175
> +#define IMX93_CLK_PDM_GATE 176
> +#define IMX93_CLK_MQS1_GATE 177
> +#define IMX93_CLK_MQS2_GATE 178
> +#define IMX93_CLK_AUD_XCVR_GATE 179
> +#define IMX93_CLK_SPDIF_GATE 180
> +#define IMX93_CLK_HSIO_32K_GATE 181
> +#define IMX93_CLK_ENET1_GATE 182
> +#define IMX93_CLK_ENET_QOS_GATE 183
> +#define IMX93_CLK_SYS_CNT_GATE 184
> +#define IMX93_CLK_TSTMR1_GATE 185
> +#define IMX93_CLK_TSTMR2_GATE 186
> +#define IMX93_CLK_TMC_GATE 187
> +#define IMX93_CLK_PMRO_GATE 188
> +#define IMX93_CLK_32K 189
> +#define IMX93_CLK_END 190
> +#endif
> --
> 2.25.1
>
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