[PATCH 7/7] arm64: dts: imx8mp-phycore-som: Set usdhc clocks
Teresa Remmet
T.Remmet at phytec.de
Tue Feb 15 01:44:21 PST 2022
Am Dienstag, dem 15.02.2022 um 09:35 +0000 schrieb Bough Chen:
> > -----Original Message-----
> > From: Teresa Remmet [mailto:t.remmet at phytec.de]
> > Sent: 2022年2月15日 17:12
> > To: linux-arm-kernel at lists.infradead.org
> > Cc: Heiko Schocher <hs at denx.de>; Jonas Kuenstler <
> > j.kuenstler at phytec.de>;
> > Bough Chen <haibo.chen at nxp.com>; dl-linux-imx <linux-imx at nxp.com>;
> > Fabio Estevam <festevam at gmail.com>; Sascha Hauer
> > <s.hauer at pengutronix.de>; Shawn Guo <shawnguo at kernel.org>; Rob
> > Herring <robh+dt at kernel.org>
> > Subject: [PATCH 7/7] arm64: dts: imx8mp-phycore-som: Set usdhc
> > clocks
> >
> > From: Jonas Kuenstler <j.kuenstler at phytec.de>
> >
> > Add missing clock assignments for eMMC node in the phyCORE-i.MX8MP
> > SoM.
> >
> > Signed-off-by: Jonas Kuenstler <j.kuenstler at phytec.de>
> > Signed-off-by: Teresa Remmet <t.remmet at phytec.de>
>
> Better to more info in the commit log, like to support HS400/HS400ES
> mode,
> and work at 200MHz DDR mode, require the
> usdhc root clock to be at least 400MHz.
Thank you very much for your quick review. I will update the commit
message in v2.
Teresa
>
> Reviewed-by: Haibo Chen <haibo.chen at nxp.com>
>
> > ---
> > arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
> > b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
> > index c471ab252a69..79b290a002c1 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
> > @@ -197,6 +197,8 @@ rv3028: rtc at 52 {
> >
> > /* eMMC */
> > &usdhc3 {
> > + assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>;
> > + assigned-clock-rates = <400000000>;
> > pinctrl-names = "default", "state_100mhz", "state_200mhz";
> > pinctrl-0 = <&pinctrl_usdhc3>;
> > pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
> > --
> > 2.25.1
--
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