[PATCH 2/7] arm64: dts: imx8mp-phycore-som: Adapt eMMC drive strength

[Bough Chen]

> -----Original Message-----
> From: Teresa Remmet [mailto:t.remmet at phytec.de]
> Sent: 2022年2月15日 17:12
> To: linux-arm-kernel at lists.infradead.org
> Cc: Heiko Schocher <hs at denx.de>; Jonas Kuenstler <j.kuenstler at phytec.de>;
> Bough Chen <haibo.chen at nxp.com>; dl-linux-imx <linux-imx at nxp.com>;
> Fabio Estevam <festevam at gmail.com>; Sascha Hauer
> <s.hauer at pengutronix.de>; Shawn Guo <shawnguo at kernel.org>; Rob
> Herring <robh+dt at kernel.org>
> Subject: [PATCH 2/7] arm64: dts: imx8mp-phycore-som: Adapt eMMC drive
> strength
> 
> Set eMMC drive strength for USDHC3_DATA lines (200Mhz) to X4 for signal
> improvement.
> 
> Signed-off-by: Teresa Remmet <t.remmet at phytec.de>

Reviewed-by: Haibo Chen <haibo.chen at nxp.com>

> ---
>  .../boot/dts/freescale/imx8mp-phycore-som.dtsi   | 16 ++++++++--------
>  1 file changed, 8 insertions(+), 8 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
> index 778f601a0119..927290990d02 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
> @@ -299,14 +299,14 @@ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
>  		fsl,pins = <
>  			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x196
>  			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d6
> -			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0
> 	0x1d6
> -			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1
> 	0x1d6
> -			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2
> 	0x1d6
> -			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3
> 	0x1d6
> -			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d6
> -			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d6
> -			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d6
> -			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d6
> +			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0
> 	0x1d2
> +			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1
> 	0x1d2
> +			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2
> 	0x1d2
> +			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3
> 	0x1d2
> +			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d2
> +			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d2
> +			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d2
> +			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d2
>  			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE
> 	0x196
>  		>;
>  	};
> --
> 2.25.1

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