[PATCH 0/8] Add APCS support for SDX65

[Rohit Agarwal]

Hello,

This series adds APCS mailbox and clock support for SDX65. The APCS IP
in SDX65 provides IPC and clock functionalities. Hence, mailbox support
is added to the "qcom-apcs-ipc-mailbox" driver and a dedicated clock
driver "apcs-sdx65" is added.

Thanks,
Rohit

Rohit Agarwal (8):
  dt-bindings: mailbox: Add binding for SDX65 APCS
  mailbox: qcom: Add support for SDX65 APCS IPC
  dt-bindings: clock: Add A7 PLL binding for SDX65
  clk: qcom: Add A7 PLL support for SDX65
  ARM: dts: qcom: sdx65: Add support for A7 PLL clock
  ARM: dts: qcom: sdx65: Add support for APCS block
  clk: qcom: Add SDX65 APCS clock controller support
  ARM: configs: qcom_defconfig: Enable SDX65 APCS clock

 .../devicetree/bindings/clock/qcom,a7pll.yaml      |   3 +-
 .../bindings/mailbox/qcom,apcs-kpss-global.yaml    |   1 +
 arch/arm/boot/dts/qcom-sdx65.dtsi                  |  17 +++
 arch/arm/configs/qcom_defconfig                    |   1 +
 drivers/clk/qcom/Kconfig                           |  15 ++-
 drivers/clk/qcom/Makefile                          |   1 +
 drivers/clk/qcom/a7-pll.c                          |   1 +
 drivers/clk/qcom/apcs-sdx65.c                      | 130 +++++++++++++++++++++
 drivers/mailbox/qcom-apcs-ipc-mailbox.c            |   5 +
 9 files changed, 170 insertions(+), 4 deletions(-)
 create mode 100644 drivers/clk/qcom/apcs-sdx65.c

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2.7.4