[PATCH v6 05/64] KVM: arm64: nv: Add EL2 system registers to vcpu context

[Miguel Luis]

Hi Marc,

> On 28 Jan 2022, at 11:18, Marc Zyngier <maz at kernel.org> wrote:
> 
> Add the minimal set of EL2 system registers to the vcpu context.
> Nothing uses them just yet.
> 
> Reviewed-by: Andre Przywara <andre.przywara at arm.com>
> Reviewed-by: Russell King (Oracle) <rmk+kernel at armlinux.org.uk>
> Signed-off-by: Marc Zyngier <maz at kernel.org>
> ---
> arch/arm64/include/asm/kvm_host.h | 33 ++++++++++++++++++++++++++++++-
> 1 file changed, 32 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
> index 115e0e2caf9a..15f690c27baf 100644
> --- a/arch/arm64/include/asm/kvm_host.h
> +++ b/arch/arm64/include/asm/kvm_host.h
> @@ -220,12 +220,43 @@ enum vcpu_sysreg {
> 	TFSR_EL1,	/* Tag Fault Status Register (EL1) */
> 	TFSRE0_EL1,	/* Tag Fault Status Register (EL0) */
> 
> -	/* 32bit specific registers. Keep them at the end of the range */
> +	/* 32bit specific registers. */
> 	DACR32_EL2,	/* Domain Access Control Register */
> 	IFSR32_EL2,	/* Instruction Fault Status Register */
> 	FPEXC32_EL2,	/* Floating-Point Exception Control Register */
> 	DBGVCR32_EL2,	/* Debug Vector Catch Register */
> 
> +	/* EL2 registers */
> +	VPIDR_EL2,	/* Virtualization Processor ID Register */
> +	VMPIDR_EL2,	/* Virtualization Multiprocessor ID Register */
> +	SCTLR_EL2,	/* System Control Register (EL2) */
> +	ACTLR_EL2,	/* Auxiliary Control Register (EL2) */
> +	HCR_EL2,	/* Hypervisor Configuration Register */
> +	MDCR_EL2,	/* Monitor Debug Configuration Register (EL2) */
> +	CPTR_EL2,	/* Architectural Feature Trap Register (EL2) */
> +	HSTR_EL2,	/* Hypervisor System Trap Register */
> +	HACR_EL2,	/* Hypervisor Auxiliary Control Register */
> +	TTBR0_EL2,	/* Translation Table Base Register 0 (EL2) */
> +	TTBR1_EL2,	/* Translation Table Base Register 1 (EL2) */
> +	TCR_EL2,	/* Translation Control Register (EL2) */
> +	VTTBR_EL2,	/* Virtualization Translation Table Base Register */
> +	VTCR_EL2,	/* Virtualization Translation Control Register */
> +	SPSR_EL2,	/* EL2 saved program status register */
> +	ELR_EL2,	/* EL2 exception link register */
> +	AFSR0_EL2,	/* Auxiliary Fault Status Register 0 (EL2) */
> +	AFSR1_EL2,	/* Auxiliary Fault Status Register 1 (EL2) */
> +	ESR_EL2,	/* Exception Syndrome Register (EL2) */
> +	FAR_EL2,	/* Hypervisor IPA Fault Address Register */

The comment for the FAR_EL2 register seems incorrect. As per D13.2.41
FAR_EL2, Fault Address Register (EL2).

Miguel