[RFC PATCH 1/2] perf: arm_spe: Fix consistency of PMSCR register bit CX

[Leo Yan]

Hi German,

On Thu, Feb 10, 2022 at 05:23:50PM +0000, German Gomez wrote:

[...]

> >>>> One way to fix this is by caching the value of the CX bit during the
> >>>> initialization of the PMU event, so that it remains consistent for the
> >>>> duration of the session.
> >>>>
> >>>> [...]
> > So the patch makes sense to me.  Just a minor comment:
> >
> > Here we can define a u64 for recording pmscr value rather than a
> > bool value.
> >
> > struct arm_spe_pmu {
> >     ...
> >     u64 pmscr;
> > };
> 
> I agree with the comment from Will that it makes more sense to store the
> value of the register in the perf_event somehow (due to misunderstanding
> from my side, I thought arm_spe_pmu struct was local to the session).

It's shame that I miss this point :) As you said, struct arm_spe_pmu is
a data structure for Arm SPE device driver instance and it's not
allocated for perf session.

> What about perf_event's void *pmu_private?

Before we use perf_event::pmu_private, could you check the data
structure arm_spe_pmu_buf firstly?  This data structure is allocated
when setup AUX ring buffer (so it's allocated for perf session).
IIUC, the function arm_spe_pmu_setup_aux() will be invoked in the perf
process, so it's good for us to initialize pmscr in this function.

Thanks,
Leo