[PATCH 4/5] arm64: dts: ti: Introduce base support for AM62x SoC

[Nishanth Menon]

On 19:10-20220209, Marc Zyngier wrote:
[...]

> > +&cbass_main {
> > +	gic500: interrupt-controller at 1800000 {
> > +		compatible = "arm,gic-v3";
> > +		#address-cells = <2>;
> > +		#size-cells = <2>;
> > +		ranges;
> > +		#interrupt-cells = <3>;
> > +		interrupt-controller;
> > +		reg = <0x00 0x01800000 0x00 0x10000>,	/* GICD */
> > +		      <0x00 0x01880000 0x00 0xC0000>;	/* GICR */
> 
> Usual rant: you are missing the GICC, GICH and GICV regions
> that are implemented by the CPU. Cortex-A53 implements them
> (they are not optional), so please describe them.
> 


-ECONFUSED. TRM for GIC500 refers to just GICD, GICR and ITS range[1].

Same thing is indicated by Generic Interrupt Controller Architecture
Specification[2] See table 1-1 (page 23).

I think you are expecting GICV3's backward compatibility mode (Table 1-2
in page 24), But in K3 architecture, are_option meant for backward
compatibility is set to true (aka no backward compatibility). I think
this did popup sometime back as well (first k3 SoC)[3]. I think the more
clearer description is available in [4].

I believe the argumentation that GICC/H/V is mandatory for A53 if GIC500
is used is not accurate. Please correct me if I am mistaken.


[1] https://developer.arm.com/documentation/ddi0516/e/programmers-model/the-gic-500-register-map?lang=en
[2] https://developer.arm.com/documentation/ihi0069/d
[3] https://patchwork.kernel.org/project/linux-arm-kernel/patch/20180607233853.p7iw7nlxxuyi66og@kahuna/
[4] https://developer.arm.com/documentation/ddi0516/e/functional-description/operation/backwards-compatibility?lang=en

-- 
Regards,
Nishanth Menon
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