[PATCH 2/2] mfd: atmel-flexcom: Add support for lan966 flexcom shared configurations

[Kavyasree Kotagiri]

Each flexcom of LAN966 SoC has 2 chip selects. For each chip
select of each flexcom there is a configuration register
FLEXCOM_SHARED[0-4]:SS_MASK[0-1]. The width of configuration
register is 21 because there are 21 shared pins on each of
which the chip select can be mapped. Each bit of the register
represents a different FLEXCOM_SHARED pin.

Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri at microchip.com>
---
 drivers/mfd/atmel-flexcom.c | 49 +++++++++++++++++++++++++++++++++++++
 1 file changed, 49 insertions(+)

diff --git a/drivers/mfd/atmel-flexcom.c b/drivers/mfd/atmel-flexcom.c
index 559eb4d352b6..b8fc476e411d 100644
--- a/drivers/mfd/atmel-flexcom.c
+++ b/drivers/mfd/atmel-flexcom.c
@@ -27,6 +27,12 @@
 #define FLEX_MR_OPMODE_MASK	(0x3 << FLEX_MR_OPMODE_OFFSET)
 #define FLEX_MR_OPMODE(opmode)	(((opmode) << FLEX_MR_OPMODE_OFFSET) &	\
 				 FLEX_MR_OPMODE_MASK)
+#ifdef CONFIG_SOC_LAN966
+/* LAN966 register offsets */
+#define FLEX_SHRD_SS_MASK_0 0x0
+#define FLEX_SHRD_SS_MASK_1 0x4
+#define FLEX_SHRD_MASK      0x1FFFFF
+#endif
 
 struct atmel_flexcom {
 	void __iomem *base;
@@ -39,6 +45,10 @@ static int atmel_flexcom_probe(struct platform_device *pdev)
 	struct device_node *np = pdev->dev.of_node;
 	struct resource *res;
 	struct atmel_flexcom *ddata;
+#ifdef CONFIG_SOC_LAN966
+	u32 lan966x_ss_pin, lan966x_cs, val;
+	void __iomem *shared_base;
+#endif
 	int err;
 
 	ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
@@ -76,6 +86,45 @@ static int atmel_flexcom_probe(struct platform_device *pdev)
 	 */
 	writel(FLEX_MR_OPMODE(ddata->opmode), ddata->base + FLEX_MR);
 
+#ifdef CONFIG_SOC_LAN966
+	/*
+	 * Flexcom Shared Register Configurations:
+	 * In order to map chip select index X of Flexcom Y to FLEXCOM_SHARED Z,
+	 * write 0 to bit index Z of FLEXCOM_SHARED[Y]:SS_MASK[X].
+	 */
+	if (of_property_read_bool(np, "lan966x-flx-shared-cfg")) {
+		/* Shared pin */
+		err = of_property_read_u32(np, "lan966x-ss-pin", &lan966x_ss_pin);
+		if (err)
+			return err;
+
+		if (lan966x_ss_pin > 20)
+			return -EINVAL;
+
+		/* chip-select */
+		err = of_property_read_u32(np, "lan966x-cs", &lan966x_cs);
+		if (err)
+			return err;
+
+		if (lan966x_cs > 1)
+			return -EINVAL;
+
+		shared_base = devm_ioremap_resource(&pdev->dev,
+				platform_get_resource(pdev, IORESOURCE_MEM, 1));
+		if (IS_ERR(shared_base)) {
+			dev_dbg(&pdev->dev, "No Flexcom shared register config\n");
+			return PTR_ERR(shared_base);
+		}
+
+		val = ~(1 << lan966x_ss_pin) & FLEX_SHRD_MASK;
+
+		if (lan966x_cs == 0)
+			writel(val, shared_base + FLEX_SHRD_SS_MASK_0);
+		else
+			writel(val, shared_base + FLEX_SHRD_SS_MASK_1);
+	}
+#endif
+
 	clk_disable_unprepare(ddata->clk);
 
 	return devm_of_platform_populate(&pdev->dev);
-- 
2.17.1