[boot-wrapper PATCH 2/2] aarch64: Enable use of SME by EL2 and below

[Mark Brown]

On Tue, Feb 01, 2022 at 06:16:58PM +0000, Mark Rutland wrote:
> On Tue, Feb 01, 2022 at 05:21:32PM +0000, broonie at kernel.org wrote:

> > +#define ID_AA64SMFR0_EL1		s3_0_c0_c4_5
> > +#define ID_AA64SMFR0_EL1_FA64		(1UL << 63)

> For consistency with the other ID fields, I'm going to make this:

>    #define ID_AA64SMFR0_EL1_FA64		BIT(63)

> In future I'd like to split the remaining definitions using shifted bits into
> separate <register>_<field> and <register>_<field>_<value> definitions (or
> something of that rought shape) so that field boundaries are always explicit,
> but those can stay as-is for now.

Sure.  I was quite confused about the idioms for the use of BIT() in
this header since it's used for for example both ID registers and SCR
but things like the various SPSR and CPTR defines use shifts, it'd
probably be good to just use BIT() throughout.
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