[PATCH V2 2/4] ARM: dts: imx6ull-dhcom: Add DH electronics DHCOM i.MX6ULL SoM and PDK2 board
Shawn Guo
shawnguo at kernel.org
Sat Dec 31 02:01:28 PST 2022
On Wed, Nov 23, 2022 at 06:35:59PM +0100, Christoph Niedermaier wrote:
> Add support for DH electronics DHCOM SoM and PDK2 rev. 400 carrier
> board. This is an SoM with i.MX6ULL and an evaluation kit. The
> baseboard provides Ethernet, UART, USB, CAN and optional display.
>
> Signed-off-by: Christoph Niedermaier <cniedermaier at dh-electronics.com>
> ---
> Cc: Rob Herring <robh+dt at kernel.org>
> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt at linaro.org>
> Cc: Peng Fan <peng.fan at nxp.com>
> Cc: Shawn Guo <shawnguo at kernel.org>
> Cc: Marek Vasut <marex at denx.de>
> Cc: Fabio Estevam <festevam at denx.de>
> Cc: NXP Linux Team <linux-imx at nxp.com>
> Cc: kernel at dh-electronics.com
> To: linux-arm-kernel at lists.infradead.org
> ---
> V2: - Remove unnecessary status properties
> - Reorder comments in front of a block
> - Reorder compatible and reg to the beginning of a node
> ---
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/imx6ull-dhcom-pdk2.dts | 222 +++++++++++
> arch/arm/boot/dts/imx6ull-dhcom-som.dtsi | 633 +++++++++++++++++++++++++++++++
> arch/arm/boot/dts/imx6ull-dhcor-som.dtsi | 251 ++++++++++++
> 4 files changed, 1107 insertions(+)
> create mode 100644 arch/arm/boot/dts/imx6ull-dhcom-pdk2.dts
> create mode 100644 arch/arm/boot/dts/imx6ull-dhcom-som.dtsi
> create mode 100644 arch/arm/boot/dts/imx6ull-dhcor-som.dtsi
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 90bb9866cc88..2cdc53211fc9 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -739,6 +739,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
> imx6ull-colibri-wifi-eval-v3.dtb \
> imx6ull-colibri-wifi-iris.dtb \
> imx6ull-colibri-wifi-iris-v2.dtb \
> + imx6ull-dhcom-pdk2.dtb \
> imx6ull-jozacp.dtb \
> imx6ull-kontron-bl.dtb \
> imx6ull-myir-mys-6ulx-eval.dtb \
> diff --git a/arch/arm/boot/dts/imx6ull-dhcom-pdk2.dts b/arch/arm/boot/dts/imx6ull-dhcom-pdk2.dts
> new file mode 100644
> index 000000000000..96be909dd196
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6ull-dhcom-pdk2.dts
> @@ -0,0 +1,222 @@
> +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
> +/*
> + * Copyright (C) 2022 DH electronics GmbH
> + *
> + * DHCOM iMX6ULL variant:
> + * DHCM-iMX6ULL-C080-R051-F0409-SPI-E2-CAN2-RTC-WBT-ADC-I-01D2
> + * DHCOR PCB number: 578-200 or newer
> + * DHCOM PCB number: 579-200 or newer
> + * PDK2 PCB number: 516-400 or newer
> + */
> +/dts-v1/;
> +
> +#include "imx6ull-dhcom-som.dtsi"
> +
> +/ {
> + model = "DH electronics i.MX6ULL DHCOM on Premium Developer Kit (2)";
> + compatible = "dh,imx6ull-dhcom-pdk2", "dh,imx6ull-dhcom-som",
> + "dh,imx6ull-dhcor-som", "fsl,imx6ull";
> +
> + clk_ext_audio_codec: clock-codec {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <24000000>;
> + };
> +
> + display_bl: display-bl {
> + compatible = "pwm-backlight";
> + brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>;
> + default-brightness-level = <8>;
> + enable-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>; /* GPIO G */
> + power-supply = <®_panel_3v3>;
> + pwms = <&pwm1 0 50000 PWM_POLARITY_INVERTED>;
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> +
> + button-0 {
> + gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; /* GPIO A */
> + label = "TA1-GPIO-A";
> + linux,code = <KEY_A>;
> + wakeup-source;
> + };
> +
> + button-1 {
> + gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; /* GPIO B */
> + label = "TA2-GPIO-B";
> + linux,code = <KEY_B>;
> + wakeup-source;
> + };
> +
> + button-2 {
> + gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; /* GPIO C */
> + label = "TA3-GPIO-C";
> + linux,code = <KEY_C>;
> + wakeup-source;
> + };
> +
> + button-3 {
> + gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; /* GPIO D */
> + label = "TA4-GPIO-D";
> + linux,code = <KEY_D>;
> + wakeup-source;
> + };
> + };
> +
> + led: led {
> + compatible = "gpio-leds";
> +
> + /*
> + * Disable PDK2 LED5, because GPIO E is
> + * already used as touch interrupt.
> + */
> + led-0 {
> + color = <LED_COLOR_ID_GREEN>;
> + default-state = "off";
> + function = LED_FUNCTION_INDICATOR;
> + function-enumerator = <5>; /* PDK2 LED5 */
> + gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; /* GPIO E */
> + status = "disabled";
> + };
> +
> + led-1 {
> + color = <LED_COLOR_ID_GREEN>;
> + default-state = "off";
> + function = LED_FUNCTION_INDICATOR;
> + function-enumerator = <6>; /* PDK2 LED6 */
> + gpios = <&gpio5 7 GPIO_ACTIVE_HIGH>; /* GPIO F */
> + };
> +
> + /*
> + * Disable PDK2 LED7, because GPIO H is
> + * already used for WiFi pin WL_REG_ON.
> + */
> + led-2 {
> + color = <LED_COLOR_ID_GREEN>;
> + default-state = "off";
> + function = LED_FUNCTION_INDICATOR;
> + function-enumerator = <7>; /* PDK2 LED7 */
> + gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; /* GPIO H */
> + status = "disabled";
> + };
> +
> + /*
> + * Disable PDK2 LED8, because GPIO I is
> + * already used for BT pin BT_REG_ON.
> + */
> + led-3 {
> + color = <LED_COLOR_ID_GREEN>;
> + default-state = "off";
> + function = LED_FUNCTION_INDICATOR;
> + function-enumerator = <8>; /* PDK2 LED8 */
> + gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; /* GPIO I */
> + status = "disabled";
> + };
> + };
> +
> + panel {
> + compatible = "edt,etm0700g0edh6";
> + backlight = <&display_bl>;
> + power-supply = <®_panel_3v3>;
> +
> + port {
> + lcd_panel_in: endpoint {
> + remote-endpoint = <&lcd_display_out>;
> + };
> + };
> + };
> +
> + /* Filtered supply voltage */
> + reg_pdk2_24v: regulator-pdk2-24v {
> + compatible = "regulator-fixed";
> + regulator-always-on;
> + regulator-max-microvolt = <24000000>;
> + regulator-min-microvolt = <24000000>;
> + regulator-name = "24V_PDK2";
> + };
> +
> + /* PDK2 U35 */
> + reg_pdk2_3v3: regulator-pdk2-3v3 {
> + compatible = "regulator-fixed";
> + regulator-always-on;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "3V3_PDK2";
> + vin-supply = <®_pdk2_24v>;
> + };
> +
> + /* 560-200 U1 */
> + reg_panel_3v3: regulator-panel-3v3 {
> + compatible = "regulator-fixed";
> + regulator-always-on;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "3V3_PANEL";
> + vin-supply = <®_pdk2_24v>;
> + };
> +
> + sound {
> + compatible = "simple-audio-card";
> + simple-audio-card,bitclock-master = <&dailink_master>;
> + simple-audio-card,format = "i2s";
> + simple-audio-card,frame-master = <&dailink_master>;
> + simple-audio-card,name = "sgtl5000";
> + simple-audio-card,routing =
> + "MIC_IN", "Mic Jack",
> + "Mic Jack", "Mic Bias",
> + "LINE_IN", "Line In Jack",
> + "Headphone Jack", "HP_OUT";
> + simple-audio-card,widgets =
> + "Microphone", "Mic Jack",
> + "Line", "Line In Jack",
> + "Headphone", "Headphone Jack";
> +
> + simple-audio-card,cpu {
> + sound-dai = <&sai2>;
> + };
> +
> + dailink_master: simple-audio-card,codec {
> + clocks = <&clk_ext_audio_codec>;
> + sound-dai = <&sgtl5000>;
> + };
> + };
> +};
> +
> +/* DHCOM I2C1 */
> +&i2c2 {
> + sgtl5000: codec at a {
audio-codec for node name.
> + compatible = "fsl,sgtl5000";
> + reg = <0x0a>;
> + #sound-dai-cells = <0>;
> + clocks = <&clk_ext_audio_codec>;
> + VDDA-supply = <®_pdk2_3v3>;
> + VDDIO-supply = <®_pdk2_3v3>;
> + };
> +
> + touchscreen at 38 {
> + compatible = "edt,edt-ft5x06";
> + reg = <0x38>;
> + interrupt-parent = <&gpio5>;
> + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */
> + power-supply = <®_panel_3v3>;
> + };
> +};
> +
> +&lcdif {
> + status = "okay";
> +
> + port {
> + lcd_display_out: endpoint {
> + remote-endpoint = <&lcd_panel_in>;
> + };
> + };
> +};
> +
> +&pwm1 {
> + status = "okay";
> +};
> +
> +&sai2 {
> + status = "okay";
> +};
> diff --git a/arch/arm/boot/dts/imx6ull-dhcom-som.dtsi b/arch/arm/boot/dts/imx6ull-dhcom-som.dtsi
> new file mode 100644
> index 000000000000..0f339a9ec252
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6ull-dhcom-som.dtsi
> @@ -0,0 +1,633 @@
> +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
> +/*
> + * Copyright (C) 2022 DH electronics GmbH
> + */
> +
> +#include "imx6ull-dhcor-som.dtsi"
> +
> +/ {
> + aliases {
> + /delete-property/ mmc0; /* Avoid double definitions */
> + /delete-property/ mmc1;
> + /delete-property/ spi2;
> + /delete-property/ spi3;
> + i2c0 = &i2c2;
> + i2c1 = &i2c1;
> + mmc2 = &usdhc2;
> + rtc0 = &rtc_i2c;
> + rtc1 = &snvs_rtc;
> + serial0 = &uart1;
> + serial1 = &uart6; /* DHCOM UART2, special hardware required */
> + serial2 = &uart3;
> + serial3 = &uart2; /* Use BT UART always as ttymxc3 */
> + serial4 = &uart4;
> + serial5 = &uart5;
> + spi0 = &ecspi1;
> + spi1 = &ecspi4; /* DHCOM SPI2, special hardware required */
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + reg_ext_3v3_ref: regulator-ext-3v3-ref {
> + compatible = "regulator-fixed";
> + regulator-always-on;
> + regulator-max-microvolt = <3300000>;
> + regulator-min-microvolt = <3300000>;
> + regulator-name = "VCC_3V3_REF";
> + };
> +
> + reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
> + compatible = "regulator-fixed";
> + regulator-max-microvolt = <5000000>;
> + regulator-min-microvolt = <5000000>;
> + regulator-name = "usb-otg1-vbus";
> + };
> +
> + reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
> + compatible = "regulator-fixed";
> + gpio = <&gpio1 5 GPIO_ACTIVE_LOW>;
> + regulator-max-microvolt = <5000000>;
> + regulator-min-microvolt = <5000000>;
> + regulator-name = "usb-otg2-vbus";
> + };
> +
> + /* SoM with WiFi/BT: WiFi pin WL_REG_ON is connected to a DHCOM GPIO */
> + /omit-if-no-ref/ usdhc1_pwrseq: usdhc1-pwrseq {
> + compatible = "mmc-pwrseq-simple";
> + reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; /* GPIO H */
> + };
> +};
> +
> +/* SoM with WiFi/BT: BT pin BT_REG_ON is connected to a DHCOM GPIO */
> +&bluetooth {
> + shutdown-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; /* GPIO I */
> +};
> +
> +&can1 {
> + pinctrl-0 = <&pinctrl_flexcan1>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +/*
> + * The signals for CAN2 TX and RX are routed to the DHCOM UART1 RTS/CTS pins.
> + * Only if this pins are used as CAN interface enable it on board layer.
> + */
> +&can2 {
> + pinctrl-0 = <&pinctrl_flexcan2>;
> + pinctrl-names = "default";
> +};
> +
> +/* DHCOM SPI1 */
> +&ecspi1 {
> + cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
> + pinctrl-0 = <&pinctrl_ecspi1>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +/*
> + * DHCOM SPI2
> + * Special hardware required that uses the pins of FEC2. Therefore this SPI
> + * interface can only be used if FEC2 is disabled.
> + */
> +&ecspi4 {
> + cs-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
> + pinctrl-0 = <&pinctrl_ecspi4>;
> + pinctrl-names = "default";
> +};
> +
> +/* DHCOM ETH1 */
> +&fec1 {
> + phy-handle = <&mdio2_phy0>;
> + phy-mode = "rmii";
> + pinctrl-0 = <&pinctrl_fec1>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +/* DHCOM ETH2 */
> +&fec2 {
> + phy-handle = <&mdio2_phy1>;
> + phy-mode = "rmii";
> + pinctrl-0 = <&pinctrl_fec2>;
> + pinctrl-names = "default";
> + status = "okay";
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + mdio2_phy0: ethernet-phy at 0 {
> + compatible = "ethernet-phy-id0007.c0f0", /* SMSC LAN8710Ai */
> + "ethernet-phy-ieee802.3-c22";
> + reg = <0>;
> + clock-names = "rmii-ref";
> + clocks = <&clks IMX6UL_CLK_ENET_REF>;
> + interrupt-parent = <&gpio5>;
> + interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
> + pinctrl-0 = <&pinctrl_fec1_phy &pinctrl_snvs_fec1_phy>;
> + pinctrl-names = "default";
> + reset-assert-us = <500>;
> + reset-deassert-us = <500>;
> + reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
> + smsc,disable-energy-detect; /* Make plugin detection reliable */
> + };
> +
> + mdio2_phy1: ethernet-phy at 1 {
> + compatible = "ethernet-phy-id0007.c0f0", /* SMSC LAN8710Ai */
> + "ethernet-phy-ieee802.3-c22";
> + reg = <1>;
> + clock-names = "rmii-ref";
> + clocks = <&clks IMX6UL_CLK_ENET2_REF>;
> + interrupt-parent = <&gpio5>;
> + interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
> + pinctrl-0 = <&pinctrl_fec2_phy &pinctrl_snvs_fec2_phy>;
> + pinctrl-names = "default";
> + reset-assert-us = <500>;
> + reset-deassert-us = <500>;
> + reset-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
> + smsc,disable-energy-detect; /* Make plugin detection reliable */
> + };
> + };
> +};
> +
> +&gpio1 {
> + gpio-line-names =
> + "", "", "", "",
> + "", "", "", "",
> + "", "", "", "DHCOM-INT",
> + "", "", "", "",
> + "", "", "DHCOM-I", "",
> + "", "", "", "",
> + "", "", "", "",
> + "", "", "", "";
> + pinctrl-0 = <&pinctrl_spi1_switch
> + &pinctrl_dhcom_i &pinctrl_dhcom_int>;
> + pinctrl-names = "default";
> +};
> +
> +&gpio4 {
> + gpio-line-names =
> + "", "", "", "",
> + "", "", "", "",
> + "", "", "", "",
> + "", "", "", "",
> + "", "DHCOM-L", "DHCOM-K", "DHCOM-M",
> + "DHCOM-J", "DHCOM-U", "DHCOM-T", "DHCOM-S",
> + "DHCOM-R", "DHCOM-Q", "DHCOM-P", "DHCOM-O",
> + "DHCOM-N", "", "", "";
> + pinctrl-0 = <&pinctrl_dhcom_j &pinctrl_dhcom_k
> + &pinctrl_dhcom_l &pinctrl_dhcom_m
> + &pinctrl_dhcom_n &pinctrl_dhcom_o
> + &pinctrl_dhcom_p &pinctrl_dhcom_q
> + &pinctrl_dhcom_r &pinctrl_dhcom_s
> + &pinctrl_dhcom_t &pinctrl_dhcom_u>;
> + pinctrl-names = "default";
> +};
> +
> +&gpio5 {
> + gpio-line-names =
> + "DHCOM-A", "DHCOM-B", "DHCOM-C", "DHCOM-D",
> + "DHCOM-E", "", "", "DHCOM-F",
> + "DHCOM-G", "DHCOM-H", "", "",
> + "", "", "", "",
> + "", "", "", "",
> + "", "", "", "",
> + "", "", "", "",
> + "", "", "", "";
> + pinctrl-0 = <&pinctrl_snvs_dhcom_a &pinctrl_snvs_dhcom_b
> + &pinctrl_snvs_dhcom_c &pinctrl_snvs_dhcom_d
> + &pinctrl_snvs_dhcom_e &pinctrl_snvs_dhcom_f
> + &pinctrl_snvs_dhcom_g &pinctrl_snvs_dhcom_h>;
> + pinctrl-names = "default";
> +};
> +
> +/* DHCOM I2C2 */
> +&i2c1 {
> + rtc_i2c: rtc at 32 {
> + compatible = "microcrystal,rv8803";
> + reg = <0x32>;
> + };
> +
> + /* Microchip 24AA025E48T-I/OT containing MAC for DHCOM ETH1 */
> + eeprom at 50 {
> + compatible = "atmel,24c02";
> + reg = <0x50>;
> + pagesize = <16>;
> + };
> +
> + /* TI ADC101C027 */
> + adc at 51 {
> + compatible = "ti,adc101c";
> + reg = <0x51>;
> + vref-supply = <®_ext_3v3_ref>;
> + };
> +
> + /* TI ADC101C027 */
> + adc at 52 {
> + compatible = "ti,adc101c";
> + reg = <0x52>;
> + vref-supply = <®_ext_3v3_ref>;
> + };
> +
> + /* Microchip 24AA025E48T-I/OT containing MAC for DHCOM ETH2 */
> + eeprom at 53 {
> + compatible = "atmel,24c02";
> + reg = <0x53>;
> + pagesize = <16>;
> + };
> +};
> +
> +/* DHCOM I2C1 */
> +&i2c2 {
> + clock-frequency = <100000>;
> + pinctrl-0 = <&pinctrl_i2c2>;
> + pinctrl-1 = <&pinctrl_i2c2_gpio>;
> + pinctrl-names = "default", "gpio";
> + scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + status = "okay";
> +};
> +
> +&lcdif {
> + pinctrl-0 = <&pinctrl_lcdif>;
> + pinctrl-names = "default";
> +};
> +
> +&pwm1 {
> + pinctrl-0 = <&pinctrl_pwm1>;
> + pinctrl-names = "default";
> +};
> +
> +&sai2 {
> + assigned-clock-rates = <320000000>;
> + assigned-clocks = <&clks IMX6UL_CLK_PLL3_PFD2>;
> + pinctrl-0 = <&pinctrl_sai2>;
> + pinctrl-names = "default";
> +};
> +
> +&tsc {
> + measure-delay-time = <0xffff>;
> + pinctrl-0 = <&pinctrl_tsc>;
> + pinctrl-names = "default";
> + pre-charge-time = <0xfff>;
> + touchscreen-average-samples = <32>;
> + xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
> +};
> +
> +/* DHCOM UART1 */
> +&uart1 {
> + pinctrl-0 = <&pinctrl_uart1>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +/*
> + * DHCOM UART2 (alternative)
> + * Special hardware required that uses DHCOM GPIO pins for DHCOM UART2.
> + * Therefore this UART interface can only be used if DHCOM GPIOs J/K/L/M are
> + * removed from GPIO hog muxing.
> + */
> +&uart6 {
> + pinctrl-0 = <&pinctrl_uart6>;
> + pinctrl-names = "default";
> + uart-has-rtscts;
> +};
> +
> +&usbotg1 {
> + adp-disable;
> + disable-over-current;
> + dr_mode = "otg";
> + hnp-disable;
> + pinctrl-0 = <&pinctrl_usbotg1>;
> + pinctrl-names = "default";
> + srp-disable;
> + vbus-supply = <®_usb_otg1_vbus>;
> + status = "okay";
> +};
> +
> +&usbotg2 {
> + disable-over-current; /* Overcurrent pin is used for TSC */
> + dr_mode = "host";
> + pinctrl-0 = <&pinctrl_usbotg2>;
> + pinctrl-names = "default";
> + tpl-support;
> + vbus-supply = <®_usb_otg2_vbus>;
> + status = "okay";
> +};
> +
> +&usbphy1 {
> + fsl,tx-d-cal = <106>;
> +};
> +
> +&usbphy2 {
> + fsl,tx-d-cal = <106>;
> +};
> +
> +/* WiFi on LGA */
> +&usdhc1 {
> + mmc-pwrseq = <&usdhc1_pwrseq>;
> +};
> +
> +/* eMMC on module */
> +&usdhc2 {
> + bus-width = <8>;
> + no-1-8-v;
> + non-removable;
> + pinctrl-0 = <&pinctrl_usdhc2>;
> + pinctrl-names = "default";
> + vmmc-supply = <&vcc_3v3>;
> + vqmmc-supply = <&vcc_3v3>;
> + status = "okay";
> +};
> +
> +&iomuxc {
> + /* DHCOM GPIOs I..U + INT_HIGHEST_PRIORITY */
> + pinctrl_dhcom_i: dhcom-i-grp {
> + fsl,pins = <MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x400120b0>;
> + };
> +
> + pinctrl_dhcom_j: dhcom-j-grp {
> + fsl,pins = <MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x400120b0>;
> + };
> +
> + pinctrl_dhcom_k: dhcom-k-grp {
> + fsl,pins = <MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x400120b0>;
> + };
> +
> + pinctrl_dhcom_l: dhcom-l-grp {
> + fsl,pins = <MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x400120b0>;
> + };
> +
> + pinctrl_dhcom_m: dhcom-m-grp {
> + fsl,pins = <MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x400120b0>;
> + };
> +
> + pinctrl_dhcom_n: dhcom-n-grp {
> + fsl,pins = <MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x400120b0>;
> + };
> +
> + pinctrl_dhcom_o: dhcom-o-grp {
> + fsl,pins = <MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x400120b0>;
> + };
> +
> + pinctrl_dhcom_p: dhcom-p-grp {
> + fsl,pins = <MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x400120b0>;
> + };
> +
> + pinctrl_dhcom_q: dhcom-q-grp {
> + fsl,pins = <MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x400120b0>;
> + };
> +
> + pinctrl_dhcom_r: dhcom-r-grp {
> + fsl,pins = <MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x400120b0>;
> + };
> +
> + pinctrl_dhcom_s: dhcom-s-grp {
> + fsl,pins = <MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x400120b0>;
> + };
> +
> + pinctrl_dhcom_t: dhcom-t-grp {
> + fsl,pins = <MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x400120b0>;
> + };
> +
> + pinctrl_dhcom_u: dhcom-u-grp {
> + fsl,pins = <MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x400120b0>;
> + };
> +
> + pinctrl_dhcom_int: dhcom-int-grp {
> + fsl,pins = <MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x400120b0>;
> + };
> +
> + pinctrl_ecspi1: ecspi1-grp {
> + fsl,pins = <
> + MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100b1
> + MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x100b1
> + MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x100b1
> + MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x1b0b0 /* SS0 */
> + >;
> + };
> +
> + pinctrl_ecspi4: ecspi4-grp {
> + fsl,pins = <
> + MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO 0x100b1
> + MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI 0x100b1
> + MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK 0x100b1
> + MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0 /* SS0 */
> + >;
> + };
> +
> + pinctrl_fec1: fec1-grp {
> + fsl,pins = <
> + /* FEC1 uses MDIO bus from FEC2 */
> + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
> + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
> + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
> + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
> + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b010
> + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b010
> + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b010
> + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b010
> + >;
> + };
> +
> + pinctrl_fec1_phy: fec1-phy-grp {
> + fsl,pins = <
> + MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0xb0 /* SMSC PHY reset */
> + >;
> + };
> +
> + pinctrl_fec2: fec2-grp {
> + fsl,pins = <
> + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
> + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
> + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
> + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
> + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
> + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
> + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b010
> + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b010
> + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b010
> + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b010
> + >;
> + };
> +
> + pinctrl_fec2_phy: fec2-phy-grp {
> + fsl,pins = <
> + MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0xb0 /* SMSC PHY reset */
> + >;
> + };
> +
> + pinctrl_flexcan1: flexcan1-grp {
> + fsl,pins = <
> + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
> + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
> + >;
> + };
> +
> + pinctrl_flexcan2: flexcan2-grp {
> + fsl,pins = <
> + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
> + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
> + >;
> + };
> +
> + pinctrl_i2c2: i2c2-grp {
> + fsl,pins = <
> + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
> + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
> + >;
> + };
> +
> + pinctrl_i2c2_gpio: i2c2-gpio-grp {
> + fsl,pins = <
> + MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001b8b0
> + MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001b8b0
> + >;
> + };
> +
> + pinctrl_lcdif: lcdif-grp {
> + fsl,pins = <
> + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
> + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
> + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
> + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
> + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
> + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
> + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
> + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
> + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
> + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
> + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
> + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
> + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
> + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
> + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
> + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
> + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
> + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
> + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
> + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
> + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
> + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
> + >;
> + };
> +
> + pinctrl_pwm1: pwm1-grp {
> + fsl,pins = <
> + MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0
> + >;
> + };
> +
> + pinctrl_sai2: sai2-grp {
> + fsl,pins = <
> + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x130b0
> + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
> + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
> + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x120b0
> + >;
> + };
> +
> + pinctrl_tsc: tsc-grp {
> + fsl,pins = <
> + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
> + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
> + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
> + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
> + >;
> + };
> +
> + pinctrl_uart1: uart1-grp {
> + fsl,pins = <
> + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
> + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
> + >;
> + };
> +
> + pinctrl_uart6: uart6-grp {
> + fsl,pins = <
> + MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1
> + MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1
> + MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS 0x1b0b1
> + MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS 0x1b0b1
> + >;
> + };
> +
> + pinctrl_usbotg1: usbotg1-grp {
> + fsl,pins = <
> + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
> + >;
> + };
> +
> + pinctrl_usbotg2: usbotg2-grp {
> + fsl,pins = <
> + MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x120b0
> + >;
> + };
> +
> + pinctrl_usdhc2: usdhc2-grp {
> + fsl,pins = <
> + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
> + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
> + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
> + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
> + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
> + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
> + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
> + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
> + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
> + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
> + MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17059 /* SD2 Reset */
> + >;
> + };
> +};
> +
> +&iomuxc_snvs {
> + /* DHCOM GPIOs A..H */
> + pinctrl_snvs_dhcom_a: snvs-dhcom-a-grp {
> + fsl,pins = <MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x400120b0>;
> + };
> +
> + pinctrl_snvs_dhcom_b: snvs-dhcom-b-grp {
> + fsl,pins = <MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x400120b0>;
> + };
> +
> + pinctrl_snvs_dhcom_c: snvs-dhcom-c-grp {
> + fsl,pins = <MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x400120b0>;
> + };
> +
> + pinctrl_snvs_dhcom_d: snvs-dhcom-d-grp {
> + fsl,pins = <MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x400120b0>;
> + };
> +
> + pinctrl_snvs_dhcom_e: snvs-dhcom-e-grp {
> + fsl,pins = <MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x400120b0>;
> + };
> +
> + pinctrl_snvs_dhcom_f: snvs-dhcom-f-grp {
> + fsl,pins = <MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x400120b0>;
> + };
> +
> + pinctrl_snvs_dhcom_g: snvs-dhcom-g-grp {
> + fsl,pins = <MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x400120b0>;
> + };
> +
> + pinctrl_snvs_dhcom_h: snvs-dhcom-h-grp {
> + fsl,pins = <MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x400120b0>;
> + };
> +
> + pinctrl_snvs_fec1_phy: snvs-fec1-phy-grp {
> + fsl,pins = <
> + MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0xb1 /* SMSC PHY Int */
> + >;
> + };
> +
> + pinctrl_snvs_fec2_phy: snvs-fec2-phy-grp {
> + fsl,pins = <
> + MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0xb1 /* SMSC PHY Int */
> + >;
> + };
> +};
> diff --git a/arch/arm/boot/dts/imx6ull-dhcor-som.dtsi b/arch/arm/boot/dts/imx6ull-dhcor-som.dtsi
> new file mode 100644
> index 000000000000..c2235f6da232
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6ull-dhcor-som.dtsi
> @@ -0,0 +1,251 @@
> +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
> +/*
> + * Copyright (C) 2022 DH electronics GmbH
> + */
> +
> +#include <dt-bindings/clock/imx6ul-clock.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/leds/common.h>
> +#include <dt-bindings/pwm/pwm.h>
> +#include "imx6ull.dtsi"
> +
> +/ {
> + memory at 80000000 {
> + /* Appropriate memory size will be filled by U-Boot */
> + reg = <0x80000000 0>;
> + device_type = "memory";
> + };
> +};
> +
> +&cpu0 {
> + fsl,soc-operating-points = <
> + /* KHz uV */
> + 900000 1250000
> + 792000 1250000
> + 528000 1175000
> + 396000 1175000
> + 198000 1175000
> + >;
> + operating-points = <
> + /* kHz uV */
> + 900000 1275000
> + 792000 1250000
> + 528000 1175000
> + 396000 1025000
> + 198000 950000
> + >;
What's changed from the standard SoC operating-points? Could you add
some comments about that?
Shawn
> +};
> +
> +&gpio1 {
> + pinctrl-0 = <&pinctrl_spi1_switch>;
> + pinctrl-names = "default";
> + /*
> + * Pin SPI_BOOT_FLASH_EN (GPIO 1.9) is a switch for either using the
> + * DHCOM SPI1 interface or accessing the SPI bootflash. Both using
> + * ecspi1, but muxed to different pins. The DHCOM SPI1 interface uses
> + * the pins PAD_LCD_DATA21..23 and the SPI bootflash uses the pins
> + * PAD_CSI_DATA04..07. If the SPI bootflash is enabled the pins for
> + * DHCOM GPIOs N/O/P/Q/R/S/T/U aren't usable anymore, because they
> + * are used for the bus interface to the SPI bootflash. The GPIOs are
> + * disconnected by a buffer which is also controlled via the pin
> + * SPI_BOOT_FLASH_EN. Therefore the access to the bootflash is a
> + * special case and is disabled by setting GPIO 1.9 to high.
> + */
> + spi1-switch-hog {
> + gpio-hog;
> + gpios = <9 0>;
> + output-high;
> + line-name = "spi1-switch";
> + };
> +};
> +
> +&i2c1 {
> + clock-frequency = <100000>;
> + pinctrl-0 = <&pinctrl_i2c1>;
> + pinctrl-1 = <&pinctrl_i2c1_gpio>;
> + pinctrl-names = "default", "gpio";
> + scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + status = "okay";
> +
> + pmic at 58 {
> + compatible = "dlg,da9061";
> + reg = <0x58>;
> +
> + onkey {
> + compatible = "dlg,da9061-onkey", "dlg,da9062-onkey";
> + status = "disabled";
> + };
> +
> + regulators {
> + vdd_soc_in_1v4: buck1 {
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-max-microvolt = <1400000>;
> + regulator-min-microvolt = <1400000>;
> + regulator-name = "vdd_soc_in_1v4";
> + };
> +
> + vcc_3v3: buck2 {
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-max-microvolt = <3300000>;
> + regulator-min-microvolt = <3300000>;
> + regulator-name = "vcc_3v3";
> + };
> +
> + /*
> + * The current DRR3 memory can be supplied with a
> + * voltage of either 1.35V or 1.5V. For reasons of
> + * backward compatibility to only 1.5V DDR3 memory,
> + * the voltage is set to 1.5V.
> + */
> + vcc_ddr_1v35: buck3 {
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-max-microvolt = <1500000>;
> + regulator-min-microvolt = <1500000>;
> + regulator-name = "vcc_ddr_1v35";
> + };
> +
> + vcc_2v5: ldo1 {
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-max-microvolt = <2500000>;
> + regulator-min-microvolt = <2500000>;
> + regulator-name = "vcc_2v5";
> + };
> +
> + vdd_snvs_in_3v3: ldo2 {
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-max-microvolt = <3300000>;
> + regulator-min-microvolt = <3300000>;
> + regulator-name = "vdd_snvs_in_3v3";
> + };
> +
> + vcc_1v8: ldo3 {
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-max-microvolt = <1800000>;
> + regulator-min-microvolt = <1800000>;
> + regulator-name = "vcc_1v8";
> + };
> +
> + vcc_1v2: ldo4 {
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-max-microvolt = <1200000>;
> + regulator-min-microvolt = <1200000>;
> + regulator-name = "vcc_1v2";
> + };
> + };
> +
> + thermal {
> + compatible = "dlg,da9061-thermal", "dlg,da9062-thermal";
> + status = "disabled";
> + };
> +
> + watchdog {
> + compatible = "dlg,da9061-watchdog", "dlg,da9062-watchdog";
> + status = "disabled";
> + };
> + };
> +};
> +
> +&ocotp {
> + /* Don't get write access by default */
> + read-only;
> +};
> +
> +®_arm {
> + vin-supply = <&vdd_soc_in_1v4>;
> +};
> +
> +®_soc {
> + vin-supply = <&vdd_soc_in_1v4>;
> +};
> +
> +/* BT on LGA (BT_REG_ON is connected to LGA pin E1) */
> +&uart2 {
> + pinctrl-0 = <&pinctrl_uart2>;
> + pinctrl-names = "default";
> + uart-has-rtscts;
> + status = "okay";
> +
> + /*
> + * Actually, the maximum speed of the chip is 4MBdps, but there are
> + * limitations that prevent this speed. It hasn't yet been figured out
> + * what the reason for this is. Currently, the maximum speed of 3MBdps
> + * can be used without any problems. If the limitation can be overcome,
> + * the speed can be increased accordingly.
> + */
> + bluetooth: bluetooth {
> + compatible = "brcm,bcm43430a1-bt"; /* muRata 1DX */
> + max-speed = <3000000>;
> + vbat-supply = <&vcc_3v3>;
> + vddio-supply = <&vcc_3v3>;
> + };
> +};
> +
> +/* WiFi on LGA (WL_REG_ON is connected to LGA pin E3) */
> +&usdhc1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + bus-width = <4>;
> + no-1-8-v;
> + non-removable;
> + keep-power-in-suspend;
> + pinctrl-0 = <&pinctrl_usdhc1_wifi>;
> + pinctrl-names = "default";
> + wakeup-source;
> + status = "okay";
> +
> + brcmf: wifi at 1 {
> + compatible = "brcm,bcm4329-fmac"; /* muRata 1DX */
> + reg = <1>;
> + };
> +};
> +
> +&iomuxc {
> + pinctrl_i2c1: i2c1-grp {
> + fsl,pins = <
> + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
> + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
> + >;
> + };
> +
> + pinctrl_i2c1_gpio: i2c1-gpio-grp {
> + fsl,pins = <
> + MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0
> + MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0
> + >;
> + };
> +
> + pinctrl_spi1_switch: spi1-switch-grp {
> + fsl,pins = <
> + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x120b0 /* SPI_BOOT_FLASH_EN */
> + >;
> + };
> +
> + pinctrl_uart2: uart2-grp {
> + fsl,pins = <
> + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
> + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
> + MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1
> + MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1
> + >;
> + };
> +
> + pinctrl_usdhc1_wifi: usdhc1-wifi-grp {
> + fsl,pins = <
> + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x1b0b0
> + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10010
> + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x1b0b0
> + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x1b0b0
> + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x1b0b0
> + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x1b0b0
> + >;
> + };
> +};
> --
> 2.11.0
>
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