[PATCH v2 04/14] arm64/sysreg: Add definitions for immediate versions of MSR ALLINT

[Mark Brown]

On Wed, Dec 07, 2022 at 07:18:35PM +0000, Marc Zyngier wrote:
> Mark Brown <broonie at kernel.org> wrote:

> > > > +#define SYS_ALLINT_CLR			sys_reg(0, 1, 4, 0, 0)
> > > > +#define SYS_ALLINT_SET			sys_reg(0, 1, 4, 1, 0)

> > > This only covers the immediate versions of ALLINT, and misses the
> > > definition for the register version, aka sys_reg(3, 0, 4, 3, 0).

> > That is already present upstream, we only need to add the immediate
> > versions which the generated header stuff doesn't have any model for
> > yet.

> Ah, missed that one, thanks.

> Out of curiosity, what is missing in the generator to deal with this
> stuff?

We'll need to teach it about registers that don't have any bitfields
defined, at the minute it requires that all the bits in the register are
specified but these don't have anything to specify.  Instead the value
written is part of the register encoding and can they only be used in a
MSR with IIRC only xzr valid as the source register.
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