[PATCH v3 1/5] dt-bindings: thermal: imx8mm-thermal: Document optional nvmem-cells

[Daniel Lezcano]

On 02/12/2022 17:23, Marek Vasut wrote:
> The TMU TASR, TCALIVn, TRIM registers must be explicitly programmed with
> calibration values from OCOTP. Document optional phandle to OCOTP nvmem
> provider.
> 
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
> Signed-off-by: Marek Vasut <marex at denx.de>
>

Applied, thanks

-- 
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog