[PATCH] arm64: dts: imx8mp: Add SNVS LPGPR

[Marek Vasut]

On 8/24/22 07:51, Alexander Stein wrote:
> Hello Marek,

Hi,

> Am Dienstag, 23. August 2022, 18:56:02 CEST schrieb Marek Vasut:
>> Add SNVS LPGPR bindings to MX8M Plus, the LPGPR is used to store
>> e.g. boot counter.

[...]

>> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
>> b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index
>> f7adcb2c14880..21689e9e68170 100644
>> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
>> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
>> @@ -478,6 +478,11 @@ snvs_pwrkey: snvs-powerkey {
>>   					wakeup-source;
>>   					status = "disabled";
>>   				};
>> +
>> +				snvs_lpgpr: snvs-lpgpr {
>> +					compatible =
> "fsl,imx8mp-snvs-lpgpr",
>> +						
> "fsl,imx7d-snvs-lpgpr";
>> +				};
>>   			};
>>
>>   			clk: clock-controller at 30380000 {
> 
> Do you have any information that the i.MX8M Plus actually has the HPLR
> register (at offset 0)? This is used in snvs_lpgpr_write. I can't find it in
> the RM, although GPR_SL is referenced in LPGPRx register description.

It seems the HPLR is only documented in the Security RM (MX8MMSRM, 
MX8MPSRM etc), not in the regular RM (MX8MMRM, MX8MPRM etc) . So it 
seems the register does exist, including the soft lock bit, it is only 
omitted from the plain RM.

(also, sorry for the delayed reply)