[PATCH] arm64/cache: Fix cache_type_cwg() for register generation

[Mark Brown]

On Thu, Aug 18, 2022 at 02:20:18PM +0100, Mark Rutland wrote:
> On Wed, Aug 17, 2022 at 07:22:26PM +0100, Mark Brown wrote:
> > On Wed, Aug 17, 2022 at 05:56:24PM +0100, Mark Rutland wrote:

> > > | #define CTR_CWG(ctr)          SYS_FIELD_GET(CTR_EL0, CWG, ctr)

> > I think if we're going to define that sort of per bitfield accessor
> > macro (which is certainly a valid and reasonable thing to do) we should
> > be having the script generate them rather than open coding them but
> > that's getting out of scope for a fix and should be done separately.

> I'm not asking for us to do that for *every* bitfield accessor, I'm just asking
> for us to be locally consistent within cache.h.

If we're going to introduce that sort of rule it should probably be a
general thing rather than a per header thing, the CTR_L1IP() thing was
a preexisting thing that was just converted in place rather than a style
we were trying to say was a good idea that should be replicated.

> I'm also happy to use SYS_FIELD_GET() directly within cache_type_cwg(), and not
> define CTR_CWG().

Sure, that's less problematic and indeed currently going through my
testing.
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