[PATCH] arm64/cache: Fix cache_type_cwg() for register generation

[Mark Rutland]

On Wed, Aug 17, 2022 at 05:02:46PM +0100, Mark Brown wrote:
> Ard noticed that since we converted CTR_EL0 to automatic generation we have
> been seeing errors on some systems handling the value of cache_type_cwg()
> such as
> 
>    CPU features: No Cache Writeback Granule information, assuming 128
> 
> This is because the manual definition of CTR_EL0_CWG_MASK was done without
> a shift while our convention is to define the mask after shifting. This
> means that the user in cache_type_cwg() was broken as it was written for
> the manually written shift then mask. Fix this by reversing, we don't use
> SYS_FIELD_GET() since that is defined in sysreg.h which we don't want to
> include in cache.h.
> 
> The only other field where the _MASK for this register is used is IminLine
> which is at offset 0 so unaffected.
> 
> Fixes: 9a3634d02301 ("arm64/sysreg: Convert CTR_EL0 to automatic generation")
> Reported-by: Ard Biesheuvel <ardb at kernel.org>
> Signed-off-by: Mark Brown <broonie at kernel.org>
> ---
>  arch/arm64/include/asm/cache.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h
> index 119e4aa02eb1..8445a3213b2f 100644
> --- a/arch/arm64/include/asm/cache.h
> +++ b/arch/arm64/include/asm/cache.h
> @@ -67,7 +67,7 @@ static __always_inline int icache_is_vpipt(void)
>  
>  static inline u32 cache_type_cwg(void)
>  {
> -	return (read_cpuid_cachetype() >> CTR_EL0_CWG_SHIFT) & CTR_EL0_CWG_MASK;
> +	return (read_cpuid_cachetype() & CTR_EL0_CWG_MASK) >> CTR_EL0_CWG_SHIFT;
>  }

Can we follow the example of:

  5b345e39d3ebc213 ("arm64/sysreg: Standardise naming for CTR_EL0 fields")

... and instead have:

| #define CTR_CWG(ctr)          SYS_FIELD_GET(CTR_EL0, CWG, ctr)

... and:

| static inline u32 cache_type_cwg(void)
| {
| 	return CTR_CWG(read_cpuid_cachetype());
| }

... since AFAICT we had SYS_FIELD_GET() available in commit 

  9a3634d02301 ("arm64/sysreg: Convert CTR_EL0 to automatic generation")

... and then it's all consistent and there's no confusion about how to apply
MASK and SHIFT.

With that:

  Acked-by: Mark Rutland <mark.rutland at arm.com>

Thanks,
Mark.