[PATCH V2] clk: imx8mp: tune the order of enet_qos_root_clk

[Abel Vesa]

On 22-08-15 07:59:06, Peng Fan wrote:
> Abel,
> 
> > Subject: Re: [PATCH V2] clk: imx8mp: tune the order of enet_qos_root_clk
> > 
> > On 22-08-15 09:34:28, Peng Fan (OSS) wrote:
> > > From: Peng Fan <peng.fan at nxp.com>
> > >
> > > The enet_qos_root_clk takes sim_enet_root_clk as parent. When
> > > registering enet_qos_root_clk, it will be put into clk orphan list,
> > > because sim_enet_root_clk is not ready.
> > >
> > > When sim_enet_root_clk is ready, clk_core_reparent_orphans_nolock will
> > > set enet_qos_root_clk parent to sim_enet_root_clk.
> > >
> > > Because CLK_OPS_PARENT_ENABLE is set, sim_enet_root_clk will be
> > > enabled and disabled during the enet_qos_root_clk reparent phase.
> > >
> > > All the above are correct. But with M7 booted early and using enet, M7
> > > enet feature will be broken, because clk driver probe phase disable
> > > the needed clks, in case M7 firmware not configure sim_enet_root_clk.
> > >
> > > And tune the order would also save cpu cycles.
> > >
> > > Reviewed-by: Ye Li <ye.li at nxp.com>
> > > Signed-off-by: Peng Fan <peng.fan at nxp.com>
> > 
> > Reviewed-by: Abel Vesa <abel.vesa at nxp.com>
> Wrong address?

vim macro issue. Sorry about that.

Reviewed-by: Abel Vesa <abel.vesa at linaro.org>

> 
> Thanks,
> Peng.
> > 
> > > ---
> > >
> > > V2:
> > >  Use Abel's new address
> > >
> > > V1:
> > >  Patch got reviewed in NXP internal.
> > >
> > >  drivers/clk/imx/clk-imx8mp.c | 2 +-
> > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/clk/imx/clk-imx8mp.c
> > > b/drivers/clk/imx/clk-imx8mp.c index e89db568f5a8..652ae58c2735
> > 100644
> > > --- a/drivers/clk/imx/clk-imx8mp.c
> > > +++ b/drivers/clk/imx/clk-imx8mp.c
> > > @@ -665,8 +665,8 @@ static int imx8mp_clocks_probe(struct
> > platform_device *pdev)
> > >  	hws[IMX8MP_CLK_CAN1_ROOT] =
> > imx_clk_hw_gate2("can1_root_clk", "can1", ccm_base + 0x4350, 0);
> > >  	hws[IMX8MP_CLK_CAN2_ROOT] =
> > imx_clk_hw_gate2("can2_root_clk", "can2", ccm_base + 0x4360, 0);
> > >  	hws[IMX8MP_CLK_SDMA1_ROOT] =
> > imx_clk_hw_gate4("sdma1_root_clk", "ipg_root", ccm_base + 0x43a0, 0);
> > > -	hws[IMX8MP_CLK_ENET_QOS_ROOT] =
> > imx_clk_hw_gate4("enet_qos_root_clk", "sim_enet_root_clk", ccm_base +
> > 0x43b0, 0);
> > >  	hws[IMX8MP_CLK_SIM_ENET_ROOT] =
> > > imx_clk_hw_gate4("sim_enet_root_clk", "enet_axi", ccm_base + 0x4400,
> > > 0);
> > > +	hws[IMX8MP_CLK_ENET_QOS_ROOT] =
> > > +imx_clk_hw_gate4("enet_qos_root_clk", "sim_enet_root_clk", ccm_base
> > +
> > > +0x43b0, 0);
> > >  	hws[IMX8MP_CLK_GPU2D_ROOT] =
> > imx_clk_hw_gate4("gpu2d_root_clk", "gpu2d_core", ccm_base + 0x4450, 0);
> > >  	hws[IMX8MP_CLK_GPU3D_ROOT] =
> > imx_clk_hw_gate4("gpu3d_root_clk", "gpu3d_core", ccm_base + 0x4460, 0);
> > >  	hws[IMX8MP_CLK_UART1_ROOT] =
> > imx_clk_hw_gate4("uart1_root_clk",
> > > "uart1", ccm_base + 0x4490, 0);
> > > --
> > > 2.37.1
> > >