[PATCH 0/9] KVM: arm64: PMU: Fixing chained events, and PMUv3p5 support

[Marc Zyngier]

Ricardo recently reported[1] that our PMU emulation was busted when it
comes to chained events, as we cannot expose the overflow on a 32bit
boundary (which the architecture requires).

This series aims at fixing this (by deleting a lot of code), and as a
bonus adds support for PMUv3p5, as this requires us to fix a few more
things.

Tested on A53 (PMUv3) and FVP (PMUv3p5).

[1] https://lore.kernel.org/r/20220805004139.990531-1-ricarkol@google.com

Marc Zyngier (9):
  KVM: arm64: PMU: Align chained counter implementation with
    architecture pseudocode
  KVM: arm64: PMU: Distinguish between 64bit counter and 64bit overflow
  KVM: arm64: PMU: Only narrow counters that are not 64bit wide
  KVM: arm64: PMU: Add counter_index_to_*reg() helpers
  KVM: arm64: PMU: Simplify setting a counter to a specific value
  KVM: arm64: PMU: Move the ID_AA64DFR0_EL1.PMUver limit to VM creation
  KVM: arm64: PMU: Allow ID_AA64DFR0_EL1.PMUver to be set from userspace
  KVM: arm64: PMU: Implement PMUv3p5 long counter support
  KVM: arm64: PMU: Allow PMUv3p5 to be exposed to the guest

 arch/arm64/include/asm/kvm_host.h |   1 +
 arch/arm64/kvm/arm.c              |   6 +
 arch/arm64/kvm/pmu-emul.c         | 372 ++++++++++--------------------
 arch/arm64/kvm/sys_regs.c         |  65 +++++-
 include/kvm/arm_pmu.h             |  16 +-
 5 files changed, 208 insertions(+), 252 deletions(-)

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2.34.1