[PATCH] arm64: dts: imx8m: correct usb power domain

[Frieder Schrempf]

Am 29.04.22 um 09:43 schrieb Li Jun:
> pgc_otg1/2 is for each usb phy and pgc_hsiomix is shared
> by 2 usb controllers, so assign those power domains to
> correct controller and phy node, decouple the pgc_otg1/2
> from pgc_hsiomix since there is no hardware dependency.
> 
> Suggested-by: Jacky Bai <ping.bai at nxp.com>
> Signed-off-by: Li Jun <jun.li at nxp.com>

Thanks for the patch!

In my previous test I probably made some mistake. The second USB
controller was kept enabled by the onboard hub. When I disable the
second port and test the patch with the first port only, resuming from
autosuspend still doesn't work, even when I keep the HSIOMIX as parent
for OTG1/2. So there's probably still something missing...

> ---
>  arch/arm64/boot/dts/freescale/imx8mm.dtsi | 8 ++++----
>  arch/arm64/boot/dts/freescale/imx8mn.dtsi | 4 ++--
>  2 files changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index 1ee05677c2dd..3ff71ca122e4 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -275,6 +275,7 @@ usbphynop1: usbphynop1 {
>  		clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
>  		assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
>  		assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
> +		power-domains = <&pgc_otg1>;
>  		clock-names = "main_clk";
>  	};
>  
> @@ -284,6 +285,7 @@ usbphynop2: usbphynop2 {
>  		clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
>  		assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
>  		assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
> +		power-domains = <&pgc_otg2>;
>  		clock-names = "main_clk";
>  	};
>  
> @@ -669,13 +671,11 @@ pgc_pcie: power-domain at 1 {
>  					pgc_otg1: power-domain at 2 {
>  						#power-domain-cells = <0>;
>  						reg = <IMX8MM_POWER_DOMAIN_OTG1>;
> -						power-domains = <&pgc_hsiomix>;
>  					};
>  
>  					pgc_otg2: power-domain at 3 {
>  						#power-domain-cells = <0>;
>  						reg = <IMX8MM_POWER_DOMAIN_OTG2>;
> -						power-domains = <&pgc_hsiomix>;
>  					};
>  
>  					pgc_gpumix: power-domain at 4 {
> @@ -1180,7 +1180,7 @@ usbotg1: usb at 32e40000 {
>  				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
>  				phys = <&usbphynop1>;
>  				fsl,usbmisc = <&usbmisc1 0>;
> -				power-domains = <&pgc_otg1>;
> +				power-domains = <&pgc_hsiomix>;
>  				status = "disabled";
>  			};
>  
> @@ -1200,7 +1200,7 @@ usbotg2: usb at 32e50000 {
>  				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
>  				phys = <&usbphynop2>;
>  				fsl,usbmisc = <&usbmisc2 0>;
> -				power-domains = <&pgc_otg2>;
> +				power-domains = <&pgc_hsiomix>;
>  				status = "disabled";
>  			};
>  
> diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> index 8def5d679e7e..5482180236ae 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> @@ -662,7 +662,6 @@ pgc_hsiomix: power-domain at 0 {
>  					pgc_otg1: power-domain at 1 {
>  						#power-domain-cells = <0>;
>  						reg = <IMX8MN_POWER_DOMAIN_OTG1>;
> -						power-domains = <&pgc_hsiomix>;
>  					};
>  
>  					pgc_gpumix: power-domain at 2 {
> @@ -1076,7 +1075,7 @@ usbotg1: usb at 32e40000 {
>  				assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>;
>  				phys = <&usbphynop1>;
>  				fsl,usbmisc = <&usbmisc1 0>;
> -				power-domains = <&pgc_otg1>;
> +				power-domains = <&pgc_hsiomix>;
>  				status = "disabled";
>  			};
>  
> @@ -1174,6 +1173,7 @@ usbphynop1: usbphynop1 {
>  		clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
>  		assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
>  		assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
> +		power-domains = <&pgc_otg1>;
>  		clock-names = "main_clk";
>  	};
>  };