[PATCH 2/2] clk: imx8mq: Enable no longer handled gates

[Sascha Hauer]

Handling of the divided pll output gates in CCM_ANALOG_SYS_PLL1_GEN_CTRL
was removed in c586f53ae159c. We shouldn't assume these gates are at
their reset-default enabled state. Enable them to let the kernel work
when the bootloader has changed the values.

Fixes: c586f53ae159c ("clk: imx8mq: remove SYS PLL 1/2 clock gates")
Reported-by: David Jander <david at protonic.nl>
Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/clk/imx/clk-imx8mq.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
index 83cc2b1c32947..55b72ff0c6a41 100644
--- a/drivers/clk/imx/clk-imx8mq.c
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -286,6 +286,7 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
 	struct device *dev = &pdev->dev;
 	struct device_node *np = dev->of_node;
 	void __iomem *base;
+	u32 val;
 	int err;
 
 	clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
@@ -357,6 +358,15 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
 	hws[IMX8MQ_DRAM_PLL_OUT] = imx_clk_hw_sscg_pll("dram_pll_out", dram_pll_out_sels, ARRAY_SIZE(dram_pll_out_sels), 0, 0, 0, base + 0x60, CLK_IS_CRITICAL | CLK_GET_RATE_NOCACHE);
 	hws[IMX8MQ_VIDEO2_PLL_OUT] = imx_clk_hw_sscg_pll("video2_pll_out", video2_pll_out_sels, ARRAY_SIZE(video2_pll_out_sels), 0, 0, 0, base + 0x54, 0);
 
+	/*
+	 * The gates in CCM_ANALOG_SYS_PLL_CFG0 are not handled by the driver,
+	 * make sure they are all enabled.
+	 */
+	val = readl(base + 0x30);
+	val |= BIT(9) | BIT(11) | BIT(13) | BIT(15) | BIT(17) | BIT(19) |
+	       BIT(21) | BIT(23) | BIT(25);
+	writel(val, base + 0x30);
+
 	/* SYS PLL1 fixed output */
 	hws[IMX8MQ_SYS1_PLL_40M] = imx_clk_hw_fixed_factor("sys1_pll_40m", "sys1_pll_out", 1, 20);
 	hws[IMX8MQ_SYS1_PLL_80M] = imx_clk_hw_fixed_factor("sys1_pll_80m", "sys1_pll_out", 1, 10);
@@ -368,6 +378,15 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
 	hws[IMX8MQ_SYS1_PLL_400M] = imx_clk_hw_fixed_factor("sys1_pll_400m", "sys1_pll_out", 1, 2);
 	hws[IMX8MQ_SYS1_PLL_800M] = imx_clk_hw_fixed_factor("sys1_pll_800m", "sys1_pll_out", 1, 1);
 
+	/*
+	 * The gates in CCM_ANALOG_SYS_PLL2_CFG0 are not handled by the driver,
+	 * make sure they are all enabled.
+	 */
+	val = readl(base + 0x3c);
+	val |= BIT(9) | BIT(11) | BIT(13) | BIT(15) | BIT(17) | BIT(19) |
+	       BIT(21) | BIT(23) | BIT(25);
+	writel(val, base + 0x3c);
+
 	/* SYS PLL2 fixed output */
 	hws[IMX8MQ_SYS2_PLL_50M] = imx_clk_hw_fixed_factor("sys2_pll_50m", "sys2_pll_out", 1, 20);
 	hws[IMX8MQ_SYS2_PLL_100M] = imx_clk_hw_fixed_factor("sys2_pll_100m", "sys2_pll_out", 1, 10);
-- 
2.30.2