[PATCH v3 7/9] x86: Add hardware prefetch control support for x86

[tarumizu.kohei at fujitsu.com]

> Prefetch control is supported on a lot of CPU models and all except Xeon PHI have
> the same MSR layout. ATOMs do not support L2_ACL and DCU_IP, but that's it. So
> there is absolutely nothing broadwell specific here.
> 
> Why do we need six explicit functions, which are pretty much copy and paste?

There is no special reason for them. My design was not good.

> The only difference is the bit they operate on. It's just a matter of proper wrapper
> structs.
> 
> See? One show() and one store() function which operates directly at the attribute
> level and supports all known variants of bits in the control MSR. No magic global
> constants, no visible management, no hardcoded type/level relations... Simple
> and straight forward.
> 
> All what the core code needs to do is to populate the attributes in the
> sys/.../cache/index$N/ directories when level and type matches.
> 
> I'm pretty sure you can simplify the A64FX code in a very similar way.

Thank you for showing me a concrete example. The implementation image
is now clear. With this in mind, I would like to simplify the core,
x86 and A64FX codes.