[PATCH v4 4/8] arm64: Add sysreg header generation scripting

[Mark Brown]

On Thu, Apr 21, 2022 at 10:47:42AM +0100, Mark Rutland wrote:
> On Tue, Apr 19, 2022 at 11:43:25AM +0100, Mark Brown wrote:

> > | #define ID_AA64ISAR0_EL1_RNDR                   ARM64_SYSREG_BITMASK(63, 60)
> > | #define ID_AA64ISAR0_EL1_RNDR_MASK              ARM64_SYSREG_BITMASK(63, 60)

> I think this got missed when s/ARM64_SYSREG_BITMASK()/GENMASK_ULL()/ happened.

Yes.

> > | #define ID_AA64ISAR0_EL1_RNDR_SHIFT             60
> > | #define ID_AA64ISAR0_EL1_RNDR_WIDTH             4
> > | #define ID_AA64ISAR0_EL1_RNDR_NI                ULL(0b0000)
> > | #define ID_AA64ISAR0_EL1_RNDR_IMP               ULL(0b0001)

> Just to check, was there a reason for going for ULL() and GENMASK_ULL() rather
> than UL() and GENMASK()?

> We generally use UL() today, since we treat `unsigned long` as the native
> register size.

That's not been updated from what you originally had had, I think I'd
just been under the impression that there was a good reason for it that
wasn't apparent to me.

> > The script requires that all bits in the register be specified and that
> > there be no overlapping fields. This helps the script spot errors in the
> > input but means that the few registers which change layout at runtime
> > depending on things like virtualisation settings will need some manual
> > handling. No actual register conversions are done here but a header for
> > the register data with some documention of the format is provided.

> It would be good to see an example of how we'd handle one of those, in case
> that means we need to play around with naming or structure of the definitions a
> bit.

My thinking here was that we might not want to handle those registers
through the automated stuff at all.  I haven't yet come up with
something that seems tasteful and viable for them, if I had a firm idea
for what that should look like I'd probably have implemented it.
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