[xilinx-xlnx:master 340/710] drivers/phy/xilinx/xilinx_dpgtquadphy.c:49:17: error: implicit declaration of function 'FIELD_PREP'

[kernel test robot]

Hi Jagadeesh,

FYI, the error/warning still remains.

tree:   https://github.com/Xilinx/linux-xlnx master
head:   0f679761fee0a4b81b4b9b7f7e1bed6eca1cd59e
commit: a2af060c77e92bff35d0f7176cc5139115ff29b9 [340/710] phy: Add driver for GTQUAD BASE for Displayport
config: arc-allyesconfig (https://download.01.org/0day-ci/archive/20220412/202204120946.PKRB8WPG-lkp@intel.com/config)
compiler: arceb-elf-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/Xilinx/linux-xlnx/commit/a2af060c77e92bff35d0f7176cc5139115ff29b9
        git remote add xilinx-xlnx https://github.com/Xilinx/linux-xlnx
        git fetch --no-tags xilinx-xlnx master
        git checkout a2af060c77e92bff35d0f7176cc5139115ff29b9
        # save the config file to linux build tree
        mkdir build_dir
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=arc SHELL=/bin/bash

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp at intel.com>

All errors (new ones prefixed by >>):

   drivers/phy/xilinx/xilinx_dpgtquadphy.c: In function 'xdpgtquad_init':
>> drivers/phy/xilinx/xilinx_dpgtquadphy.c:49:17: error: implicit declaration of function 'FIELD_PREP' [-Werror=implicit-function-declaration]
      49 |         data |= FIELD_PREP(GT_QUAD_BASE_CH1_CLK_DIV_MASK,
         |                 ^~~~~~~~~~
   cc1: some warnings being treated as errors


vim +/FIELD_PREP +49 drivers/phy/xilinx/xilinx_dpgtquadphy.c

    34	
    35	static int xdpgtquad_init(struct phy *phy)
    36	{
    37		struct dpgtquadphy_dev *gtquad = phy_get_drvdata(phy);
    38		u32 data;
    39	
    40		/*
    41		 * Unlocking the NPI space so that GT CH1 divider value can be
    42		 * programmed. This will generate a /20 clk
    43		 */
    44		writel(GT_QUAD_BASE_CTL_VALUE,
    45		       gtquad->base + GT_QUAD_BASE_CTL);
    46	
    47		data = readl(gtquad->base + GT_QUAD_BASE_CH1_CLK_DIV_REG);
    48		data &= ~GT_QUAD_BASE_CH1_CLK_DIV_MASK;
  > 49		data |= FIELD_PREP(GT_QUAD_BASE_CH1_CLK_DIV_MASK,
    50				   GT_QUAD_BASE_CH1_CLK_DIV_VALUE);
    51		writel(data, gtquad->base + GT_QUAD_BASE_CH1_CLK_DIV_REG);
    52	
    53		return 0;
    54	}
    55	

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