[PATCH 3/3] arm64: dts: nuvoton: Add initial support for MA35D1

Jacky Huang ychuang3 at nuvoton.com
Tue Apr 5 19:58:59 PDT 2022



On 2022/3/7 下午 06:25, Krzysztof Kozlowski wrote:
> On 07/03/2022 10:19, Jacky Huang wrote:
>> Add the initial device tree files for Nuvoton MA35D1 Soc.
>>
>> Signed-off-by: Jacky Huang <ychuang3 at nuvoton.com>
>> ---
>>   arch/arm64/boot/dts/Makefile               |   1 +
>>   arch/arm64/boot/dts/nuvoton/Makefile       |   2 +
>>   arch/arm64/boot/dts/nuvoton/ma35d1-evb.dts |  23 +++++
>>   arch/arm64/boot/dts/nuvoton/ma35d1.dtsi    | 106 +++++++++++++++++++++
>>   4 files changed, 132 insertions(+)
>>   create mode 100644 arch/arm64/boot/dts/nuvoton/Makefile
>>   create mode 100644 arch/arm64/boot/dts/nuvoton/ma35d1-evb.dts
>>   create mode 100644 arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
>> index 639e01a4d855..28e01442094f 100644
>> --- a/arch/arm64/boot/dts/Makefile
>> +++ b/arch/arm64/boot/dts/Makefile
>> @@ -30,3 +30,4 @@ subdir-y += synaptics
>>   subdir-y += ti
>>   subdir-y += toshiba
>>   subdir-y += xilinx
>> +subdir-y += nuvoton
>> diff --git a/arch/arm64/boot/dts/nuvoton/Makefile b/arch/arm64/boot/dts/nuvoton/Makefile
>> new file mode 100644
>> index 000000000000..e1e0c466bf5e
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/nuvoton/Makefile
>> @@ -0,0 +1,2 @@
>> +# SPDX-License-Identifier: GPL-2.0
>> +dtb-$(CONFIG_ARCH_NUVOTON) += ma35d1-evb.dtb
> ARCH_NUVOTON does not exist.

I would add the following to end of arch/arm64/Kconfig.platforms, and 
add the
modification to this patch series.

config ARCH_MA35D1
     bool "Nuvoton MA35D1 SOC Family"
     select PINCTRL
     select PINCTRL_MA35D1
     select PM
     select GPIOLIB
     select SOC_BUS
     select VIDEOMODE_HELPERS
     select FB_MODE_HELPERS
     help
       This enables support for Nuvoton MA35D1 SOC Family.


>> diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-evb.dts b/arch/arm64/boot/dts/nuvoton/ma35d1-evb.dts
>> new file mode 100644
>> index 000000000000..38e4f734da0f
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/nuvoton/ma35d1-evb.dts
>> @@ -0,0 +1,23 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Device Tree Source for MA35D1 Evaluation Board (EVB)
>> + *
>> + * Copyright (C) 2021 Nuvoton Technology Corp.
>> + */
>> +
>> +/dts-v1/;
>> +#include "ma35d1.dtsi"
>> +
>> +/ {
>> +       model = "Nuvoton MA35D1-EVB";
>> +
>> +       chosen {
>> +               bootargs = "console=ttyS0,115200n8";
> No bootargs. "chosen", please.

OK, I would modify it as:

chosen {
         stdout-path = "serial0:115200n8";
     };


>> +       };
> You need compatible and bindings.

I will add the compatible here
compatible = "nuvoton,ma35d1-evb", "nuvoton,ma35d1"

And, I should create a new binding file 
Documentation/devicetree/bindings/arm/nuvoton.yaml to this patch series.
And the property would be:

properties:
   compatible:
     description: Nuvoton MA35D1-EVB
     items:
       - const: nuvoton,ma35d1-evb
       - const: nuvoton,ma35d1


Is it OK?

>> +
>> +       memory at 80000000 {
>> +               device_type = "memory";
>> +               reg = <0x00000000 0x80000000 0 0x10000000>;
>> +       };
>> +};
>> +
>> diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
>> new file mode 100644
>> index 000000000000..27adac4975c3
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
>> @@ -0,0 +1,106 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Copyright (c) 2022 Nuvoton Technology Corp.
>> + */
>> +
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/input/input.h>
>> +#include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
>> +
>> +/ {
>> +       compatible = "nuvoton,ma35d1";
> Please run checkpatch. This compatible looks undocumented.

I will create a new binding file 
Documentation/devicetree/bindings/arm/nuvoton.yaml to this patch series.


>> +       interrupt-parent = <&gic>;
>> +       #address-cells = <2>;
>> +       #size-cells = <2>;
>> +
>> +       cpus {
>> +               #address-cells = <2>;
>> +               #size-cells = <0>;
>> +               cpu-map {
>> +                       cluster0 {
>> +                               core0 {
>> +                                       cpu = <&cpu0>;
>> +                               };
>> +                               core1 {
>> +                                       cpu = <&cpu1>;
>> +                               };
>> +                       };
>> +               };
> Line break between each nodes, here and below.

OK, I will fix it in the next version.

>
>> +               cpu0: cpu at 0 {
>> +                       device_type = "cpu";
>> +                       compatible = "arm,cortex-a35";
>> +                       reg = <0x0 0x0>;
>> +                       enable-method = "psci";
>> +                       next-level-cache = <&L2_0>;
>> +               };
>> +               cpu1: cpu at 1 {
>> +                       device_type = "cpu";
>> +                       compatible = "arm,cortex-a35";
>> +                       reg = <0x0 0x1>;
>> +                       enable-method = "psci";
>> +                       next-level-cache = <&L2_0>;
>> +               };
>> +               L2_0: l2-cache0 {
>> +                       compatible = "cache";
>> +                       cache-level = <2>;
>> +               };
>> +       };
>> +
>> +       psci {
>> +               compatible = "arm,psci-0.2";
>> +               method = "smc";
>> +       };
>> +
>> +       timer {
>> +               compatible = "arm,armv8-timer";
>> +               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
>> +                                         IRQ_TYPE_LEVEL_LOW)>,
>> +                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
>> +                                         IRQ_TYPE_LEVEL_LOW)>,
>> +                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
>> +                                         IRQ_TYPE_LEVEL_LOW)>,
>> +                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
>> +                                         IRQ_TYPE_LEVEL_LOW)>;
>> +               clock-frequency = <12000000>;
>> +       };
>> +
>> +       sys: system-controller at 40460000 {
>> +               compatible = "nuvoton,ma35d1-sys", "syscon", "simple-mfd";
>> +               reg = <0x0 0x40460000 0x0 0x200>;
>> +       };
>> +
>> +       reset: reset-controller {
>> +               compatible = "nuvoton,ma35d1-reset";
>> +               nuvoton,ma35d1-sys = <&sys>;
>> +               #reset-cells = <1>;
>> +       };
>> +
>> +       clk: clock-controller at 40460200 {
>> +               compatible = "nuvoton,ma35d1-clk";
>> +               reg = <0x00000000 0x40460200 0x0 0x100>;
>> +               #clock-cells = <1>;
>> +               assigned-clocks = <&clk DDRPLL>,
>> +                                 <&clk APLL>,
>> +                                 <&clk EPLL>,
>> +                                 <&clk VPLL>;
>> +               assigned-clock-rates = <266000000>,
>> +                                      <180000000>,
>> +                                      <500000000>,
>> +                                      <102000000>;
>> +               clock-pll-mode = <1>, <0>, <0>, <0>;
>> +       };
>> +
>> +       gic: interrupt-controller at 50800000 {
>> +               compatible = "arm,gic-400";
>> +               #interrupt-cells = <3>;
>> +               interrupt-parent = <&gic>;
>> +               interrupt-controller;
>> +               reg = <0x0 0x50801000 0 0x1000>,
>> +                     <0x0 0x50802000 0 0x2000>,
>> +                     <0x0 0x50804000 0 0x2000>,
>> +                     <0x0 0x50806000 0 0x2000>;
>> +               interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0x13) |
>> +                                        IRQ_TYPE_LEVEL_HIGH)>;
>> +       };
>> +};
>> --
>> 2.17.1
>>
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>
>> Your cooperation is highly appreciated...
> Cooperation seems futile... :)
>
> Best regards,
> Krzysztof

I am sorry. I have requested mail server manager to add exception rule.
The unpleasant official declarations are removed.

Thanks for your review.

Sincerely,

Jacky







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