[PATCH v2 5/8] arm64: Create cache sysfs directory without ACPI PPTT for hardware prefetch control

[tarumizu.kohei at fujitsu.com]

> What registers?

>> Hardware prefetch control driver need cache sysfs directory and cache
>> level/type information. In ARM processor, these information can be
>> obtained from the register even without PPTT.

This register mean CLIDR_EL1.

> CCSIDR register is no longer used. You must use DT or PPTT.

I know that commit "a8d4636f96ad" (arm64: cacheinfo: Remove CCSIDR-based
cache information probing) removed the code to read the CCSIDR from the
kernel.
Therefore, I only use level and type information that can be read from
CLIDR_EL1. Are there similar concerns when using only CLIDR_EL1
information?