[arm:clearfog 12/13] drivers/pci/pcie/aspm.c:581 pcie_aspm_cap_init() warn: inconsistent indenting

kernel test robot lkp at intel.com
Sat Sep 18 02:06:37 PDT 2021


tree:   git://git.armlinux.org.uk/~rmk/linux-arm.git clearfog
head:   8ad56d503152a980fe3800144ee64348c19f886e
commit: 65a0ea62b58a1e4717cf6db437c981e984d22a4a [12/13] mvebu/clearfog pcie updates
config: x86_64-randconfig-m001-20210918 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp at intel.com>

smatch warnings:
drivers/pci/pcie/aspm.c:581 pcie_aspm_cap_init() warn: inconsistent indenting

vim +581 drivers/pci/pcie/aspm.c

   542	
   543	static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
   544	{
   545		struct pci_dev *child = link->downstream, *parent = link->pdev;
   546		u32 parent_lnkcap, child_lnkcap;
   547		u16 parent_lnkctl, child_lnkctl;
   548		u32 parent_l1ss_cap, child_l1ss_cap;
   549		u32 parent_l1ss_ctl1 = 0, child_l1ss_ctl1 = 0;
   550		struct pci_bus *linkbus = parent->subordinate;
   551	
   552		if (blacklist) {
   553			/* Set enabled/disable so that we will disable ASPM later */
   554			link->aspm_enabled = ASPM_STATE_ALL;
   555			link->aspm_disable = ASPM_STATE_ALL;
   556			return;
   557		}
   558	
   559		/*
   560		 * If ASPM not supported, don't mess with the clocks and link,
   561		 * bail out now.
   562		 */
   563		pcie_capability_read_dword(parent, PCI_EXP_LNKCAP, &parent_lnkcap);
   564		pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &child_lnkcap);
   565		if (!(parent_lnkcap & child_lnkcap & PCI_EXP_LNKCAP_ASPMS))
   566			return;
   567	
   568		/* Configure common clock before checking latencies */
   569		pcie_aspm_configure_common_clock(link);
   570	
   571		/*
   572		 * Re-read upstream/downstream components' register state after
   573		 * clock configuration.  L0s & L1 exit latencies in the otherwise
   574		 * read-only Link Capabilities may change depending on common clock
   575		 * configuration (PCIe r5.0, sec 7.5.3.6).
   576		 */
   577		pcie_capability_read_dword(parent, PCI_EXP_LNKCAP, &parent_lnkcap);
   578		pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &child_lnkcap);
   579		pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &parent_lnkctl);
   580		pcie_capability_read_word(child, PCI_EXP_LNKCTL, &child_lnkctl);
 > 581	dev_info(&parent->dev, "up support %x enabled %x\n",
   582		 (parent_lnkcap & PCI_EXP_LNKCAP_ASPMS) >> 10,
   583		 !!(parent_lnkctl & PCI_EXP_LNKCTL_ASPMC));
   584	dev_info(&parent->dev, "dn support %x enabled %x\n",
   585		 (child_lnkcap & PCI_EXP_LNKCAP_ASPMS) >> 10,
   586		 !!(child_lnkctl & PCI_EXP_LNKCTL_ASPMC));
   587	
   588		/*
   589		 * Setup L0s state
   590		 *
   591		 * Note that we must not enable L0s in either direction on a
   592		 * given link unless components on both sides of the link each
   593		 * support L0s.
   594		 */
   595		if (parent_lnkcap & child_lnkcap & PCI_EXP_LNKCAP_ASPM_L0S)
   596			link->aspm_support |= ASPM_STATE_L0S;
   597	
   598		if (child_lnkctl & PCI_EXP_LNKCTL_ASPM_L0S)
   599			link->aspm_enabled |= ASPM_STATE_L0S_UP;
   600		if (parent_lnkctl & PCI_EXP_LNKCTL_ASPM_L0S)
   601			link->aspm_enabled |= ASPM_STATE_L0S_DW;
   602		link->latency_up.l0s = calc_l0s_latency(parent_lnkcap);
   603		link->latency_dw.l0s = calc_l0s_latency(child_lnkcap);
   604	
   605		/* Setup L1 state */
   606		if (parent_lnkcap & child_lnkcap & PCI_EXP_LNKCAP_ASPM_L1)
   607			link->aspm_support |= ASPM_STATE_L1;
   608	
   609		if (parent_lnkctl & child_lnkctl & PCI_EXP_LNKCTL_ASPM_L1)
   610			link->aspm_enabled |= ASPM_STATE_L1;
   611		link->latency_up.l1 = calc_l1_latency(parent_lnkcap);
   612		link->latency_dw.l1 = calc_l1_latency(child_lnkcap);
   613	
   614		/* Setup L1 substate */
   615		pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CAP,
   616				      &parent_l1ss_cap);
   617		pci_read_config_dword(child, child->l1ss + PCI_L1SS_CAP,
   618				      &child_l1ss_cap);
   619	
   620		if (!(parent_l1ss_cap & PCI_L1SS_CAP_L1_PM_SS))
   621			parent_l1ss_cap = 0;
   622		if (!(child_l1ss_cap & PCI_L1SS_CAP_L1_PM_SS))
   623			child_l1ss_cap = 0;
   624	
   625		/*
   626		 * If we don't have LTR for the entire path from the Root Complex
   627		 * to this device, we can't use ASPM L1.2 because it relies on the
   628		 * LTR_L1.2_THRESHOLD.  See PCIe r4.0, secs 5.5.4, 6.18.
   629		 */
   630		if (!child->ltr_path)
   631			child_l1ss_cap &= ~PCI_L1SS_CAP_ASPM_L1_2;
   632	
   633		if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_ASPM_L1_1)
   634			link->aspm_support |= ASPM_STATE_L1_1;
   635		if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_ASPM_L1_2)
   636			link->aspm_support |= ASPM_STATE_L1_2;
   637		if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_1)
   638			link->aspm_support |= ASPM_STATE_L1_1_PCIPM;
   639		if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_2)
   640			link->aspm_support |= ASPM_STATE_L1_2_PCIPM;
   641	
   642		if (parent_l1ss_cap)
   643			pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
   644					      &parent_l1ss_ctl1);
   645		if (child_l1ss_cap)
   646			pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL1,
   647					      &child_l1ss_ctl1);
   648	
   649		if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_1)
   650			link->aspm_enabled |= ASPM_STATE_L1_1;
   651		if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_2)
   652			link->aspm_enabled |= ASPM_STATE_L1_2;
   653		if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_1)
   654			link->aspm_enabled |= ASPM_STATE_L1_1_PCIPM;
   655		if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_2)
   656			link->aspm_enabled |= ASPM_STATE_L1_2_PCIPM;
   657	
   658		if (link->aspm_support & ASPM_STATE_L1SS)
   659			aspm_calc_l1ss_info(link, parent_l1ss_cap, child_l1ss_cap);
   660	
   661		/* Save default state */
   662		link->aspm_default = link->aspm_enabled;
   663	
   664		/* Setup initial capable state. Will be updated later */
   665		link->aspm_capable = link->aspm_support;
   666	
   667		/* Get and check endpoint acceptable latencies */
   668		list_for_each_entry(child, &linkbus->devices, bus_list) {
   669			u32 reg32, encoding;
   670			struct aspm_latency *acceptable =
   671				&link->acceptable[PCI_FUNC(child->devfn)];
   672	
   673			if (pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT &&
   674			    pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END)
   675				continue;
   676	
   677			pcie_capability_read_dword(child, PCI_EXP_DEVCAP, &reg32);
   678			/* Calculate endpoint L0s acceptable latency */
   679			encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6;
   680			acceptable->l0s = calc_l0s_acceptable(encoding);
   681			/* Calculate endpoint L1 acceptable latency */
   682			encoding = (reg32 & PCI_EXP_DEVCAP_L1) >> 9;
   683			acceptable->l1 = calc_l1_acceptable(encoding);
   684	
   685			pcie_aspm_check_latency(child);
   686		}
   687	}
   688	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
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