[v3 06/24] clk: mediatek: Add MT8195 apmixedsys clock support

[Stephen Boyd]

Quoting Chun-Jie Chen (2021-09-13 19:16:15)
> Add MT8195 apmixedsys clock controller which provides Plls
> generated from SoC 26m and ssusb clock gate control.
> 
> Signed-off-by: Chun-Jie Chen <chun-jie.chen at mediatek.com>
> Reviewed-by: Chen-Yu Tsai <wenst at chromium.org>
> ---

Applied to clk-next