[xilinx-xlnx:master 173/214] drivers/clk/clk-xlnx-clock-wizard.c:324:8: error: implicit declaration of function 'FIELD_PREP'

[kernel test robot]

tree:   https://github.com/Xilinx/linux-xlnx master
head:   6cb480b208248d57a9906d801469d7ea8292df52
commit: bf7387ee9a75c2a390b19f63c47076344e664b86 [173/214] clocking-wizard: Support higher frequency accuracy
config: i386-allyesconfig (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
        # https://github.com/Xilinx/linux-xlnx/commit/bf7387ee9a75c2a390b19f63c47076344e664b86
        git remote add xilinx-xlnx https://github.com/Xilinx/linux-xlnx
        git fetch --no-tags xilinx-xlnx master
        git checkout bf7387ee9a75c2a390b19f63c47076344e664b86
        # save the attached .config to linux build tree
        make W=1 ARCH=i386 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp at intel.com>

All errors (new ones prefixed by >>):

   drivers/clk/clk-xlnx-clock-wizard.c: In function 'clk_wzrd_dynamic_all_nolock':
>> drivers/clk/clk-xlnx-clock-wizard.c:324:8: error: implicit declaration of function 'FIELD_PREP' [-Werror=implicit-function-declaration]
     324 |  reg = FIELD_PREP(WZRD_CLKOUT_DIVIDE_MASK, clockout0_div) |
         |        ^~~~~~~~~~
   drivers/clk/clk-xlnx-clock-wizard.c: In function 'clk_wzrd_recalc_rate_all':
>> drivers/clk/clk-xlnx-clock-wizard.c:392:6: error: implicit declaration of function 'FIELD_GET' [-Werror=implicit-function-declaration]
     392 |  d = FIELD_GET(WZRD_DIVCLK_DIVIDE_MASK, reg);
         |      ^~~~~~~~~
   cc1: some warnings being treated as errors


vim +/FIELD_PREP +324 drivers/clk/clk-xlnx-clock-wizard.c

   301	
   302	static int clk_wzrd_dynamic_all_nolock(struct clk_hw *hw, unsigned long rate,
   303					       unsigned long parent_rate)
   304	{
   305		struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
   306		u32 reg, pre;
   307		u16 retries;
   308		int err;
   309		u64 vco_freq, rate_div, f, clockout0_div;
   310	
   311		err = clk_wzrd_get_divisors(hw, rate, parent_rate);
   312		if (err)
   313			pr_err("failed to get divisors\n");
   314	
   315		vco_freq = DIV_ROUND_CLOSEST((parent_rate * divider->valuem), divider->valued);
   316		rate_div = DIV_ROUND_CLOSEST((vco_freq * WZRD_FRAC_POINTS), rate);
   317	
   318		clockout0_div = rate_div / WZRD_FRAC_POINTS;
   319	
   320		pre = DIV_ROUND_CLOSEST((vco_freq * WZRD_FRAC_POINTS), rate);
   321		f = (u32)(pre - (clockout0_div * WZRD_FRAC_POINTS));
   322		f = f & WZRD_CLKOUT_FRAC_MASK;
   323	
 > 324		reg = FIELD_PREP(WZRD_CLKOUT_DIVIDE_MASK, clockout0_div) |
   325		      FIELD_PREP(WZRD_CLKOUT0_FRAC_MASK, f);
   326	
   327		writel(reg, divider->base + WZRD_CLK_CFG_REG(2));
   328		/* Set divisor and clear phase offset */
   329		reg = FIELD_PREP(WZRD_CLKFBOUT_MULT_MASK, divider->valuem) |
   330		      FIELD_PREP(WZRD_DIVCLK_DIVIDE_MASK, divider->valued);
   331		writel(reg, divider->base + WZRD_CLK_CFG_REG(0));
   332		writel(divider->valueo, divider->base + WZRD_CLK_CFG_REG(2));
   333		writel(0, divider->base + WZRD_CLK_CFG_REG(3));
   334		/* Check status register */
   335		retries = WZRD_DR_NUM_RETRIES;
   336		while (retries--) {
   337			if (readl(divider->base + WZRD_DR_STATUS_REG_OFFSET) &
   338								WZRD_DR_LOCK_BIT_MASK)
   339				break;
   340		}
   341	
   342		if (!retries)
   343			return -ETIMEDOUT;
   344	
   345		/* Initiate reconfiguration */
   346		writel(WZRD_DR_BEGIN_DYNA_RECONF,
   347		       divider->base + WZRD_DR_INIT_REG_OFFSET);
   348	
   349		/* Check status register */
   350		retries = WZRD_DR_NUM_RETRIES;
   351		while (retries--) {
   352			if (readl(divider->base + WZRD_DR_STATUS_REG_OFFSET) &
   353								WZRD_DR_LOCK_BIT_MASK)
   354				break;
   355		}
   356	
   357		if (!retries)
   358			return -ETIMEDOUT;
   359	
   360		return 0;
   361	}
   362	
   363	static int clk_wzrd_dynamic_all(struct clk_hw *hw, unsigned long rate,
   364					unsigned long parent_rate)
   365	{
   366		struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
   367		unsigned long flags = 0;
   368		int ret;
   369	
   370		if (divider->lock)
   371			spin_lock_irqsave(divider->lock, flags);
   372		else
   373			__acquire(divider->lock);
   374	
   375		ret = clk_wzrd_dynamic_all_nolock(hw, rate, parent_rate);
   376	
   377		if (divider->lock)
   378			spin_unlock_irqrestore(divider->lock, flags);
   379		else
   380			__release(divider->lock);
   381	
   382		return ret;
   383	}
   384	
   385	static unsigned long clk_wzrd_recalc_rate_all(struct clk_hw *hw,
   386						      unsigned long parent_rate)
   387	{
   388		struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
   389		u32 m, d, o, div, reg, f;
   390	
   391		reg = readl(divider->base + WZRD_CLK_CFG_REG(0));
 > 392		d = FIELD_GET(WZRD_DIVCLK_DIVIDE_MASK, reg);
   393		m = FIELD_GET(WZRD_CLKFBOUT_MULT_MASK, reg);
   394		reg = readl(divider->base + WZRD_CLK_CFG_REG(2));
   395		o = FIELD_GET(WZRD_DIVCLK_DIVIDE_MASK, reg);
   396		f = FIELD_GET(WZRD_CLKOUT0_FRAC_MASK, reg);
   397	
   398		div = DIV_ROUND_CLOSEST(d * (WZRD_FRAC_POINTS * o + f), WZRD_FRAC_POINTS);
   399		return divider_recalc_rate(hw, parent_rate * m, div, divider->table,
   400				divider->flags, divider->width);
   401	}
   402	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
-------------- next part --------------
A non-text attachment was scrubbed...
Name: .config.gz
Type: application/gzip
Size: 64505 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20211101/cb937d62/attachment-0001.gz>